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42129a?sam?06/2013 description the atmel ? sam d20 family is a series of low-power, high-performance, arm ? -based embedded flash microcontrollers based on the arm cortex ? -m0+ 32-bit processor. operating at a maximum speed of 48mhz, and with a two-stage pipeline, single-cycle i/o access, single-cycle 32x32 multiplier, event system and a fast and flexible interrupt controller, the sam d20 series microc ontrollers are highly efficient, reaching 2.14 coremark/mhz ? 0.93 dmips/mhz. all devices in the sam d20 series contain multiple instances of the serial communication interface (sercom). the sercom is a very flexible serial communication interface, configurable to operate as i 2 c, spi or usart, giving developers extended flexibility not only in the mix of serial interfaces available, but also in pcb layout. additionally, each sercom instance can be assigned to different i/o pins through i/o multiplexing, further increasing flexibility. the devices include multiple instances of 16-bit timer/counters (tc). each tc can be individually programmed to perform frequen cy and waveform generation, accurate program execution timing and input captur e with time and frequency measurement of digital signals. the tcs can be configured to operate in 8-bit and 16-bit modes, and two tcs can be cascaded to form a 32-bit tc. the sam d20 series power manager (pm) has two software-selectable sleep modes, idle and standby. the standby mode supports sleepwalking functionality, by which a peripheral can be selectively activated based on events, even when the peripheral clock is stopped. in addition the event system (evsys) supports asynchronous events, allowing peripherals to receive, react to and send events, even in standby mode. the devices feature several oscillators, such as a 48mhz digital frequency locked loop (dfll48m), 400khz ? 32mhz external crystal oscillator (xosc), 8mhz internal oscillator (osc8m), 32khz ultra-low-pow er internal oscillator (osculp32k), 32.768khz high-accuracy internal oscillator (osc32k) and 32.768khz crystal oscillator (xosc32k). any of these oscillators can be used as a source for the system clock. different clock domains can be independently configured to run at different speeds, enabling the user to save power by running each peripheral at the optimal clock frequency, and thus maintain a high cpu speed and throughput while reducing system power consumption. atmel sam d20j / sam d20g / sam d20e arm-based embedded fl ash microcontroller preliminary datasheet
2 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 features z processor z arm cortex-m0+ cpu running at up to 48mhz z single-cycle hardware multiplier z memories z 16/32/64/128/256kb in-system self-programmable flash z 2/4/8/16/32kb sram z system z power-on reset (por) and brown-out detection (bod) z internal and external clock options with 48mhz digital frequency locked loop (dfll48m) z external interrupt controller (eic) z 16 external interrupts z one non-maskable interrupt z two-pin serial wire debug (swd) programming, test and debugging interface z low power z idle and standby sleep modes z sleepwalking peripherals z peripherals z 8-channel event system z up to eight 16-bit timer/counters (tc), configurable as either: z one 16-bit tc with co mpare/capture channels z one 8-bit tc with compare/capture channels z one 32-bit tc with compare/capt ure channels, by using two tcs z 32-bit real time counter (rtc) with clock/calendar function z watchdog timer (wdt) z crc-32 generator z up to six serial communication interfaces (sercom), each configurable to operate as either: z usart with full-duplex and singl e-wire half-duplex configuration z i 2 c z spi z one 12-bit, 350ksps analog-to-digital converter (adc) with up to 20 channels z differential and single-ended channels z 1/2x to 16x gain stage z automatic offset and gain error compensation z oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution z 10-bit, 350ksps digital-to-analog converter (dac) z two analog comparators (ac) with window compare function z peripheral touch controller (ptc) z i/o z up to 52 programmable i/o lines z packages z 64-pin tqfp, qfn z 48-pin tqfp, qfn z 32-pin tqfp, qfn z operating voltage z 1.62v ? 3.63v
3 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 1. configuration summary sam d20j sam d20g sam d20e flash 256/128/64/32/16kb 256/128/64/32/16kb 128/64/32/16kb sram 32/16/8/4/2kb 32/16/8/4/2kb 16/8/4/2kb timer counter (tc) instances 8 6 6 waveform output channels per timer counter instance 2 2 2 serial communication interface (sercom) instances 6 6 4 analog-to-digital converter (adc) channels 20 14 10 analog comparators (ac) 2 2 2 digital-to-analog converter (dac) instances 1 1 1 real-time counter (rtc) instances 1 1 1 rtc alarms 1 1 1 rtc compare values 1 32-bit value or 2 16-bit values 1 32-bit value or 2 16-bit values 1 32-bit value or 2 16-bit values general purpose i/o-lines (gpios) 52 38 26 external interrupt lines 16 16 16 peripheral touch controller (ptc) x and y lines 16x16 12x10 10x6 maximum speed 48mhz number of pins 64 48 32 packages qfn tqfp qfn tqfp qfn tqfp oscillators 32.768khz crystal oscillator (xosc32k) 0.4-32mhz crystal oscillator (xosc) 32.768khz high-accuracy internal oscillator (osc32k) 32.768khz ultra-low-power internal oscillator (osculp32k) 8mhz internal oscillator (osc8m) 48mhz digital frequency locked loop (dfll48m) event system channels 8 8 8 sw debug interface 1 1 1 watchdog timer (wdt) instances 1 1 1
4 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 2. ordering information sam d20 2.1 ordering information sam d20e samd ?? 20 ?? e ?? 14 ?? a ??\??? m ?? u ?? t product ? family samd ? = ? base ? line ? microcontroller product ? series 20 ? = ? cortex ? m0+ ? cpu, ? basic ? feature ? set flash ? memory ? density 18 ? = ? 256kb 17 ? = ? 128kb 16 ? = ? 64kb 15 ? = ? 32kb 14 ? = ? 16kb product ? variant a ? = ? default ? variant pin ? count e ? = ? 32 ? pins g ? = ? 48 ? pins j ? = ? 64 ? pins package ? carrier no ? character ? = ? tray ? (default) ????????????????????? t ? = ? tape ? and ? reel package ? grade package ? type a ? = ? tqfp m ? = ? qfn c ? = ? ubga u ? = ? wlcsp u ? = ?\ 40 ?\? 85c ? matte ? sn ? plating h ? = ?\ 40 ?\? 85c ? nipdau ? plating ordering code flash (bytes) sram (bytes) package carrier type samd20e14a-au 16k 2k tqfp32 tray samd20e14a-aut tape & reel samd20e14a-mu qfn32 tray samd20e14a-mut tape & reel samd20e15a-au 32k 4k tqfp32 tray samd20e15a-aut tape & reel samd20e15a-mu qfn32 tray samd20e15a-mut tape & reel samd20e16a-au 64k 8k tqfp32 tray samd20e16a-aut tape & reel samd20e16a-mu qfn32 tray samd20e16a-mut tape & reel
5 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 2.2 ordering information sam d20g samd20e17a-au 128k 16k tqfp32 tray samd20e17a-aut tape & reel samd20e17a-mu qfn32 tray samd20e17a-mut tape & reel ordering code flash (bytes) sram (bytes) package carrier type ordering code flash (bytes) sram (bytes) package carrier type samd20g14a-au 16k 2k tqfp48 tray samd20g14a-aut tape & reel samd20g14a-mu qfn48 tray samd20g14a-mut tape & reel samd20g15a-au 32k 4k tqfp48 tray samd20g15a-aut tape & reel samd20g15a-mu qfn48 tray samd20g15a-mut tape & reel samd20g16a-au 64k 8k tqfp48 tray samd20g16a-aut tape & reel samd20g16a-mu qfn48 tray samd20g16a-mut tape & reel samd20g17a-au 128k 16k tqfp48 tray samd20g17a-aut tape & reel samd20g17a-mu qfn48 tray samd20g17a-mut tape & reel samd20g18a-au 256k 32k tqfp48 tray samd20g18a-aut tape & reel samd20g18a-mu qfn48 tray samd20g18a-mut tape & reel
6 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 2.3 ordering information sam d20j ordering code flash (bytes) sram (bytes) package carrier type samd20j14a-au 16k 2k tqfp64 tray samd20j14a-aut tape & reel samd20j14a-mu qfn64 tray SAMD20J14A-MUT tape & reel samd20j15a-au 32k 4k tqfp64 tray samd20j15a-aut tape & reel samd20j15a-mu qfn64 tray samd20j15a-mut tape & reel samd20j16a-au 64k 8k tqfp64 tray samd20j16a-aut tape & reel samd20j16a-mu qfn64 tray samd20j16a-mut tape & reel samd20j17a-au 128k 16k tqfp64 tray samd20j17a-aut tape & reel samd20j17a-mu qfn64 tray samd20j17a-mut tape & reel samd20j18a-au 256k 32k tqfp64 tray samd20j18a-aut tape & reel samd20j18a-mu qfn64 tray samd20j18a-mut tape & reel
7 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 3. about this document 3.1 conventions 3.1.1 numerical notation 3.1.2 memory size and type 3.1.3 frequency and time table 3-1. numerical notation symbol description 165 decimal number 0b0101 binary number (example 0b0101 = 5 decimal) 0101 binary numbers are given without suffix if unambiguous 0x3b24 hexadecimal number x represents an unknown or don't care value z represents a high-impedance (floating) state for either a signal or a bus table 3-2. memory size and bit rate symbol description kb/kbyte kilobyte (2 10 = 1024) mb/mbyte megabyte (2 20 = 1024*1024) gb/gbyte gigabyte (2 30 = 1024*1024*1024) b bit (binary 0 or 1) b byte (8 bits) 1kbit/s 1,000 bit/s rate (not 1,024 bit/s) 1mbit/s 1,000,000 bit/s rate 1gbit/s 1,000,000,000 bit/s rate word 32 bit half-word 16 bit table 3-3. frequency and time symbol description khz 1khz = 10 3 hz = 1,000hz mhz 10 6 = 1,000,000hz ghz 10 9 = 1,000,000,000hz s second
8 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 3.1.4 registers and bits 3.2 acronyms and abbreviations table 1-5 contains acronyms and abbreviations used in this document. ms millisecond s microsecond ns nanosecond table 3-3. frequency and time (continued) symbol description table 3-4. register and bit mnemonics symbol description r/w read/write accessible register bit. the us er can read from and write to this bit. r read-only accessible register bit. the user can only read this bit. writes will be ignored. w write-only accessible register bit. the user can only write this bit. reading this bit will return an undefined value. bit bit names are shown in uppercase. (example enable) field[n:m] a set of bits from bit n down to m. (examp le: pina[3:0] = {pina3, pina2, pina1, pina0} reserved reserved bits are unused and reserved for future use. for compatibility with future devices, always write reserved bits to zero when the register is wr itten. reserved bits will always return zero when read. peripheral i if several instances of a peripheral exist, the peripher al name is followed by a number to indicate the number of the instance in the range 0-n. peripheral0 denotes one specific instance. reset value of a register after a power reset. this is also the value of registers in a peripheral after performing a software reset of the peripheral, except for the debug control registers. set/clr registers with set/clr suffix allows the user to cl ear and set bits in a register without doing a read- modify-write operation. these registers always come in pairs. writing a one to a bit in the clr register will clear the corresponding bit in both registers, while writing a one to a bit in the set register will set the corresponding bi t in both registers. both registers will return the same value when read. if both registers ar e written simultaneously, the write to th e clr register will take precedence. table 3-5. acronyms and abbreviations abbreviation description ac analog comparator adc analog-to-digital converter addr address ahb amba advanced high-performance bus amba ? advance microcontroller bus architecture ahb amba advanced high-performance bus
9 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 apb amba advanced peripheral bus aref analog reference voltage blb boot lock bit bod brown-out detector cal calibration cc compare/capture clk clock crc cyclic redundancy check ctrl control dac digital-to-analog converter dap debug access port dfll digital frequency locked loop dsu device service unit eeprom electrically erasable programmable read-only memory eic external interrupt controller evsys event system gclk generic clock controller gnd ground gpio general purpos e input/output i 2 c inter-integrated circuit if interrupt flag int interrupt mbist memory built-in self-test mem-ap memory access port nmi non-maskable interrupt nvic nested vector interrupt controller nvm non-volatile memory nvmctrl non-volatile memory controller osc oscillator pac peripheral access controller pc program counter per period pm power manager table 3-5. acronyms and abbreviations (continued) abbreviation description
10 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 por power-on reset ptc peripheral touch controller pwm pulse width modulation ram random-access memory ref reference rtc real-time counter rx receiver/receive sercom serial communication interface smbus ? system management bus sp stack pointer spi serial peripheral interface sram static random-access memory sysctrl system controller swd serial wire debug tc timer/counter tx transmitter/transmit ulp ultra-low power usart universal synchronous and asynchronous serial receiver and transmitter v dd common voltage to be applied to vddio, vddin and vddana v ddin digital supply voltage v ddio digital supply voltage v ddana analog supply voltage vref voltage reference wdt watchdog timer xosc crystal oscillator table 3-5. acronyms and abbreviations (continued) abbreviation description
11 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 4. block diagram notes: 1. some products have different number of sercom instances, timer/counter instances, ptc signals and adc sig- nals. refer to ?configuration summary? on page 3 for details. 6 x sercom 8 x timer counter real time counter ahb/apb bridge c m s high speed bus matrix port port watchdog timer serial wire swdio nvm controller 256/128/64/32kb flash s cortex-m0+ processor f max 48mhz swclk device service unit ahb/apb bridge a adc ain[19:0] vrefa ain[3:0] s 32/16/8/4kb ram m reset controller sleep controller clock controller power manager reset 8 x timer counter event system s 6 x sercom 2 analog comparators system controller xout xin xout32 xin32 osculp32k osc32k osc8m dfll48m bod33 bod12 xosc32k xosc vref vreg generic clock x[15:0] y[15:0] peripheral touch controller peripheral access controller ahb/apb bridge b vrefp vout dac external interrupt controller peripheral access controller peripheral access controller extint[15:0] nmi gclk_io[7:0] s pad[3:0] wo[1:0] vrefb (see note1)
12 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 5. pinout diagrams 5.1 sam d20j pa00 1 pa01 2 pa02 3 pa03 4 pb04 5 pb05 6 gndana 7 vddana 8 pb06 9 pb07 10 pb08 11 pb09 12 pa04 13 pa05 14 pa06 15 pa07 16 pa08 17 pa09 18 pa10 19 pa11 20 vddio 21 gnd 22 pb10 23 pb11 24 pb12 25 pb13 26 pb14 27 pb15 28 pa12 29 pa13 30 pa14 31 pa15 32 vddio 48 gnd 47 pa25 46 pa24 45 pa23 44 pa22 43 pa21 42 pa20 41 pb17 40 pb16 39 pa19 38 pa18 37 pa17 36 pa16 35 vddio 34 gnd 33 pb22 49 pb23 50 pa27 51 reset 52 pa28 53 gnd 54 vddcor 55 vddin 56 pa30 57 pa31 58 pb30 59 pb31 60 pb00 61 pb01 62 pb02 63 pb03 64 digital pin analog pin oscillator ground input supply regulated output supply reset pin
13 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 5.2 sam d20g pa21 pa00 1 pa01 2 pa02 3 pa03 4 gndana 5 vddana 6 pb08 7 pb09 8 pa04 9 pa05 10 pa06 11 pa07 12 pa08 13 pa09 14 pa10 15 pa11 16 vddio 17 gnd 18 pb10 19 pb11 20 pa12 21 pa13 22 pa14 23 pa15 24 vddio 36 gnd 35 pa25 34 pa24 33 pa23 32 pa22 31 30 pa20 29 pa19 28 pa18 27 pa17 26 pa16 25 pb22 37 pb23 38 pa27 39 reset 40 pa28 41 gnd 42 vddcore 43 vddin 44 pa30 45 pa31 46 pb02 47 pb03 48 digital pin analog pin oscillator ground input supply regulated output supply reset pin
14 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 5.3 sam d20e pa00 1 pa01 2 pa02 3 pa03 4 pa04 5 pa05 6 pa06 7 pa07 8 vddana 9 gnd 10 pa08 11 pa09 12 pa10 13 pa11 14 pa14 15 pa15 16 pa25 24 pa24 23 pa23 22 pa22 21 pa19 20 pa18 19 pa17 18 pa16 17 pa27 25 reset 26 pa28 27 gnd 28 vddcore 29 vddin 30 pa30 31 pa31 32 digital pin analog pin oscillator ground input supply regulated output supply reset pin
15 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 6. i/o multiplexing and considerations 6.1 multiplexed signals each pin is either controlled by the port as a general purpose i/o or can be assigned to one of the peripheral functions a, b, c, d, e, f, g or h. by default, each pin is controlled by the port. to enable a peripheral function on a pin, the peripheral multiplexer enable bit in the pin configuration register corresponding to that pin (pincfgn.pmuxen, n = 0- 31) in the port must be written to one. the selection of per ipheral function a to h is done by writing to the peripheral multiplexing odd and even bits in the peripheral multiple xing register (pmu xn.pmuxe/o) in the port. refer to ?port? on page 289 for details on how to configure the i/o multiplexing. table 6-1 describes the peripheral signals multiplexed to the port i/o lines. table 6-1. port controller functi on multiplexing (sheet 1 of 2) pin i/o line supply type a b (1) c d e f g h sam d20e sam d20g sam d20j eic ref adc ac ptc dac sercom (2) tc (3) ac/gclk 1 1 1 pa00 vddana extint[0] sercom1 pad[0] tc2/wo[0] 2 2 2 pa01 vddana extint[1] sercom1 pad[1] tc2/wo[1] 3 3 3 pa02 vddana extint[2] ain[0] y[0] vout 4 4 4 pa03 vddana extint[3] adc/vrefa dac/vrefp ain[1] y[1] 5 pb04 vddana extint[4] ain[12] y[10] 6 pb05 vddana extint[5] ain[13] y[11] 9 pb06 vddana extint[6] ain[14] y[12] 10 pb07 vddana extint[7] ain[15] y[13] 7 11 pb08 vddana extint[8] ain[2] y[14] sercom4 pad[0] tc4/wo[0] 8 12 pb09 vddana extint[9] ain[3] y[15] sercom4 pad[1] tc4/wo[1] 5 9 13 pa04 vddana extint[4] adc vrefb ain[4] ain[0] y[2] sercom0 pad[0] tc0/wo[0] 6 10 14 pa05 vddana extint[5] ain[5] ain[1] y[3] sercom0 pad[1] tc0/wo[1] 7 11 15 pa06 vddana extint[6] ain[6] ain[2] y[4] sercom0 pad[2] tc1/wo[0] 8 12 16 pa07 vddana extint[7] ain[7] ain[3] y[5] sercom0 pad[3] tc1/wo[1] 11 13 17 pa08 vddio i 2 c nmi ain[16] x[0] sercom0 pad[0] sercom2 pad[0] tc0/wo[0] 12 14 18 pa09 vddio i 2 c extint[9] ain[17] x[1] sercom0 pad[1] sercom2 pad[1] tc0/wo[1] 13 15 19 pa10 vddio extint[10] ain[18] x[2] sercom0 pad[2] sercom2 pad[2] tc1/wo[0] gclk_io[4] 14 16 20 pa11 vddio extint[11] ain[19] x[3] sercom0 pad[3] sercom2 pad[3] tc1/wo[1] gclk_io[5] 19 23 pb10 vddio extint[10] sercom4 pad[2] tc5/wo[0] gclk_io[4] 20 24 pb11 vddio extint[11] sercom4 pad[3] tc5/wo[1] gclk_io[5] 25 pb12 vddio i 2 c extint[12] x[12] sercom4 pad[0] tc4/wo[0] gclk_io[6] 26 pb13 vddio i 2 c extint[13] x[13] sercom4 pad[1] tc4/wo[1] gclk_io[7] 27 pb14 vddio extint[14] x[14] sercom4 pad[2] tc5/wo[0] gclk_io[0]
16 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 note: 1. all analog pad functions are on peripheral function b. pe ripheral function b must be selected to disable the digital control of the pad. 28 pb15 vddio extint[15] x[15] sercom4 pad[3] tc5/wo[1] gclk_io[1] 21 29 pa12 vddio i 2 c extint[12] sercom2 pad[0] sercom4 pad[0] tc2/wo[0] ac/cmp[0] 22 30 pa13 vddio i 2 c extint[13] sercom2 pad[1] sercom4 pad[1] tc2/wo[1] ac/cmp[1] 15 23 31 pa14 vddio extint[14] sercom2 pad[2] sercom4 pad[2] tc3/wo[0] gclk_io[0] 16 24 32 pa15 vddio extint[15] sercom2 pad[3] sercom4 pad[3] tc3/wo[1] gclk_io[1] 17 25 35 pa16 vddio extint[0] x[4] sercom1 pad[0] sercom3 pad[0] tc2/wo[0] gclk_io[2] 18 26 36 pa17 vddio extint[1] x[5] sercom1 pad[1] sercom3 pad[1] tc2/wo[1] gclk_io[3] 19 27 37 pa18 vddio extint[2] x[6] sercom1 pad[2] sercom3 pad[2] tc3/wo[0] ac/cmp[0] 20 28 38 pa19 vddio extint[3] x[7] sercom1 pad[3] sercom3 pad[3] tc3/wo[1] ac/cmp[1] 39 pb16 vddio i 2 c extint[0] sercom5 pad[0] tc6/wo[0] gclk_io[2] 40 pb17 vddio i 2 c extint[1] sercom5 pad[1] tc6/wo[1] gclk_io[3] 29 41 pa20 vddio extint[4] x[8] sercom5 pad[2] sercom3 pad[2] tc7/wo[0] gclk_io[4] 30 42 pa21 vddio extint[5] x[9] sercom5 pad[3] sercom3 pad[3] tc7/wo[1] gclk_io[5] 21 31 43 pa22 vddio i 2 c extint[6] x[10] sercom3 pad[0] sercom5 pad[0] tc4/wo[0] gclk_io[6] 22 32 44 pa23 vddio i 2 c extint[7] x[11] sercom3 pad[1] sercom5 pad[1] tc4/wo[1] gclk_io[7] 23 33 45 pa24 vddio extint[12] sercom3 pad[2] sercom5 pad[2] tc5/wo[0] 24 34 46 pa25 vddio extint[13] sercom3 pad[3] sercom5 pad[3] tc5/wo[1] 37 49 pb22 vddio extint[6] sercom5 pad[2] tc7/wo[0] gclk_io[0] 38 50 pb23 vddio extint[7] sercom5 pad[3] tc7/wo[1] gclk_io[1] 25 39 51 pa27 vddio extint[15] gclk_io[0] 27 41 53 pa28 vddio extint[8] gclk_io[0] 31 45 57 pa30 vddio extint[10] sercom1 pad[2] tc1/wo[0] swclk gclk_io[0] 32 46 58 pa31 vddio extint[11] sercom1 pad[3] tc1/wo[1] 59 pb30 vddio i 2 c extint[14] sercom5 pad[0] tc0/wo[0] 60 pb31 vddio i 2 c extint[15] sercom5 pad[1] tc0/wo[1] 61 pb00 vddana extint[0] ain[8] y[6] sercom5 pad[2] tc7/wo[0] 62 pb01 vddana extint[1] ain[9] y[7] sercom5 pad[3] tc7/wo[1] 47 63 pb02 vddana extint[2] ain[10] y[8] sercom5 pad[0] tc6/wo[0] 48 64 pb03 vddana extint[3] ain[11] y[9] sercom5 pad[1] tc6/wo[1] table 6-1. port controller functi on multiplexing (sheet 2 of 2) pin i/o line supply type a b (1) c d e f g h sam d20e sam d20g sam d20j eic ref adc ac ptc dac sercom (2) tc (3) ac/gclk
17 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 2. only some pads can be used in sercom i 2 c mode. check the type column before trying to use a sercom pad in i 2 c mode. 3. note that tc6 and tc7 are not supported on the sam d20g. refer to ?configuration summary? on page 3 for details. 6.2 other functions 6.2.1 oscillator pinout the oscillators are not mapped to the normal port functions and their multiplexing are controlled by registers in the system controller (sysctrl). refer to ?sysctrl ? system controller? on page 132 for more information. 6.2.2 serial wire debug interface pinout only the swclk pin is mapped to the normal port functions. a debugger cold-plugging or hot-plugging detection will automatically switch the swdio port to the swdio function. refer to ?dsu ? device service unit? on page 41 for more information. oscillator supply signal i/o line xosc vddio xin pa14 xout pa15 xosc32k vddana xin32 pa00 xout32 pa01 signal supply i/o line swclk vddio pa30 swdio vddio pa31
18 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 7. signal descriptions list the following table gives details on signal names classified by peripheral. signal name function type active level comments analog comparators - ac ain3 - ain0 analog inputs analog cmp1 - cmp0 comparator outputs digital analog digital converter - adc ain19 - ain0 adc analog inputs analog vrefp adc voltage external reference analog digital analog converter - dac vout dac voltage output analog vrefp dac voltage external reference analog external interrup t controller - eic extint15 - extint0 external interrupts input nmi external non-maskable interrupt input generic clock generator - gclk gclk_io7 - gclk_io0 generic clock (source clock or generic clock generator output) i/o power manager - pm reset_n reset input low serial communication interface - sercomx pad3 - pad0 sercom i/o pads i/o system control - sysctrl xin crystal input analog/ digital xin32 32khz crystal input analog/ digital xout crystal output analog xout32 32khz crystal output analog timer counter - tcx wo1 - wo0 waveform outputs output low peripheral touch controller - ptc x15-x0 ptc input analog y15-y0 ptc input analog
19 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 general purpose i/o - port pa25 - pa00 parallel i/o controller i/o port a i/o pa28 - pa27 parallel i/o controller i/o port a i/o pa31 - pa30 parallel i/o controller i/o port a i/o pb17 - pb00 parallel i/o controller i/o port b i/o pb23 - pb22 parallel i/o controller i/o port b i/o pb31 - pb30 parallel i/o controller i/o port b i/o signal name function type active level comments
20 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 8. power supply and start-up considerations 8.1 power domain overview 8.2 power supply considerations 8.2.1 power supplies the atmel? sam d20 has several different power supply pins: z vddio: powers i/o lines, osc8m and xosc. voltage is 1.62v to 3.63v, nominal. z vddin: powers i/o lines and the internal regulator. voltage is 1.62v to 3.63v, nominal. z vddana: powers i/o lines and the adc, ac, dac, pt c, osculp32k, osc32k, xosc32k. voltage is 1.62v to 3.63v, nominal. z vddcore: internal regulated voltage output. powers the core, memories and peripherals. voltage is 1.2v, nominal. the same voltage must be applied to both vddin, vddio and vddana. this common voltage is referred to as v dd in the datasheet. voltage regulator vddin vddcore gnd adc ac dac ptc xosc32k osc32k vddana gndana pa[7:2] pb[9:0] pa[1:0] digital logic (cpu, peripherals) dfll48m vddio osc8m bod33 xosc osculp32k pa[31:16] pb[31:10] pa[15:14] bod12 por pa[13:8]
21 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 the ground pins, gnd, are common to vddcore, vddi o and vddin. the ground pin for vddana is gndana. for decoupling recommendations for the different power supplies, refer to the schematic checklist. 8.2.2 voltage regulator an embedded voltage regulator supplies all the digital logic. the voltage regulator features two different modes: z normal mode: to be used when the cpu and peripherals are running z low power (lp) mode: to be used when the regulator draws small static current. it can be used in standby mode 8.2.3 typical powering schematics the sam d20 uses a single supply from 1.62v to 3.63v. this is the recommended power supply connection. figure 8-1. power supply connection 8.2.4 power-up sequence 8.2.4.1 minimum rise rate the integrated power-on reset (por) circuitry monitoring the vddana power supply requires a minimum rise rate. 8.2.4.2 maximum rise rate to avoid risk of latch-up, the rise rate of the power supply must not exceed the values described in electrical characteristics. (1.62v 3.63v) main supply vddio vddana vddin vddcore gnd gndana sam d20
22 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 8.3 start-up considerations this section summarizes the boot sequence of the sam d20. the behavior after power-up is controlled by the power manager. for specific details, refer to ?pm ? power manager? on page 105 . 8.3.1 starting of clocks after power-up, the device will be held in its initial state by the power-on reset circuitry, until the power has stabilized throughout the device. once the power has stabilized, the device will use a 1mhz clock. this clock is derived from the 8mhz internal oscillator (osc8m), which is divided by eight and used as a clock source for generic clock generator 0. generic clock generator 0 is the main clock for the power manager (pm). on system start-up, the 48mhz digital frequency locked loop (dfll48m) is disabled. some synchronous system clocks are active, allowing software execution. refer to the ?clock mask register? section in ?pm ? power manager? on page 105 for the list of peripheral clocks running. synchronous system clocks that are running are by default not divided and receive a 1mhz clock through generic clock generator 0. all the generic clocks are disabl ed except gclk_wdt, which is used by the watchdog timer (wdt). 8.3.2 i/o pins after power-up, the i/o pins are tri-stated. 8.3.3 fetching of in itial instructions after reset has been released, the cpu starts fetching pc and sp values from the reset address, which is 0x00000000. this address points to the first executable address in the inter nal flash. the code read from the internal flash is free to configure the clock system and clock sources. refer to ?pm ? power manager? on page 105 , ?gclk ? generic clock controller? on page 83 and ?sysctrl ? system controller? on page 132 for details. refer to the arm architecture reference manual for more information on cpu startup. 8.4 power-on reset a nd brown-out detector the sam d20 embeds three features to monitor, warn and/or reset the device: z por: power-on reset on vddana z bod33: brown-out detector on vddana z bod12: brown-out detector on vddcore 8.4.1 power-on reset on vddana por monitors vddana. it is always activated and monitors voltage at startup and also during all the sleep modes. if vddana goes below the threshold voltage, the entire chip is reset. 8.4.2 brown-out detector on vddana bod33 monitors vddana. refer to ?sysctrl ? system controller? on page 132 for details. 8.4.3 brown-out detector on vddcore once the device has started up, bod12 monitors the internal vddcore. refer to ?sysctrl ? system controller? on page 132 for details.
23 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 9. product mapping figure 9-1. sam d20 product mapping this figure represents the full configuration of the atmel ? sam d20 with maximum flash and sram capabilities and a full set of peripherals. refer to the ?configuration summary? on page 3 for details. code sram undefined peripherals reserved undefined global memory space 0x00000000 0x20000000 0x20008000 0x40000000 0x43000000 0x60000000 0x60000200 0xffffffff internal sram sram 0x20000000 0x20008000 peripheral bridge a peripheral bridge b peripheral bridge c peripherals 0x40000000 0x41000000 0x42000000 0x42ffffff reserved pac0 pm sysctrl gclk wdt rtc eic peripheral bridge a 0x40000000 0x40000400 0x40000800 0x40000c00 0x40001000 0x40001400 0x40001800 0x40ffffff 0x40001c00 peripheral bridge b reserved pac1 dsu nvmctrl port 0x41000000 0x41002000 0x41004000 0x41004400 0x41ffffff 0x41004800 internal flash code 0x00000000 0x00040000 0x1fffffff reserved sercom5 pac2 evsys sercom0 sercom1 sercom2 sercom3 sercom4 peripheral bridge c tc7 tc0 tc1 tc2 tc3 tc4 tc5 tc6 adc ac 0x42000000 0x42000400 0x42000800 0x42000c00 0x42001000 0x42001400 0x42001800 0x42002000 0x42001c00 0x42003000 0x42003400 0x42003800 0x42003c00 0x42004000 0x42004400 0x42004800 reserved 0x42ffffff dac 0x42004c00 0x42002400 0x42002800 0x42002c00 ptc 0x42005000 reserved system 0xe0000000 scs reserved reserved rom table reserved system 0xe0000000 0xe000e000 0xe000f000 0xe00ff000 0xe0100000 0xffffffff
24 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 10. memories 10.1 embedded memories z internal high-speed flash z internal high-speed ram, single-cycle access at full speed z dedicated flash area for eeprom emulation 10.2 physical memory map the high-speed bus is implemented as a bus matrix. refer to ?high-speed bus matrix? on page 29 for details. all high- speed bus addresses are fixed, and they are never remapped in any way, even during boot. the 32-bit physical address space is mapped as follows: table 10-1. sam d20 physical memory map (1) note: 1. x = g, j or e. samd20e18 is not available. refer to ?ordering information sam d20? on page 4 for details. table 10-2. flash memory parameters (1) notes: 1. x = g, j or e. samd20e18 is not available. refer to ?ordering information sam d20? on page 4 for details. 2. the number of pages (nvmp) and page size (psz) c an be read from the nvm pages and page size bits in the nvm parameter register in the nvmctrl (param.nvm p and param.psz, respectively). refer to param for details. memory start address size samd20x18 samd20x17 samd20x16 samd20x15 samd20x14 embedded flash 0x00000000 256kb 128kb 64kb 32kb 16kb embedded sram 0x20000000 32kb 16kb 8kb 4kb 2kb peripheral bridge a 0x40000000 64kb 64kb 64kb 64kb 64kb peripheral bridge b 0x41000000 64kb 64kb 64kb 64kb 64kb peripheral bridge c 0x42000000 64kb 64kb 64kb 64kb 64kb device flash size number of pages (nvmp) page size (psz) row size samd20x18 256kb 4096 64 bytes 4 pages = 256 bytes samd20x17 128kb 2048 64 bytes 4 pages = 256 bytes samd20x16 64kb 1024 64 bytes 4 pages = 256 bytes samd20x15 32kb 512 64 bytes 4 pages = 256 bytes samd20x14 16kb 256 64 bytes 4 pages = 256 bytes
25 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 10.3 non-volatile memory (nvm) user row mapping the nvm user row contains calibration data that are automatically read at device power on. the nvm user row can be read at address 0x804000. to write the nvm user row refer to ?nvmctrl ? non-volatile memory controller? on page 266 . note that when writing to the user row the values will only be loaded at device reset. table 10-3. nvm user row mapping bit position name description 2:0 bootprot used to select one of eight different bootloader sizes. refer to ?nvmctrl ? non-volatile memory controller? on page 266 . 3 reserved 6:4 eeprom used to select one of eight different eeprom area sizes<. refer to ?nvmctrl ? non-volatile memory controller? on page 266 . 7 reserved 13:8 bod33 level bod33 threshold level (bod33.l evel) at power on. refer to bod33 register. 14 bod33 enable bod33 enable at power on. refer to bod33 register. 16:15 bod33 action bod33 action at power on. refer to bod33 register. 21:17 bod12 level bod12 threshold level at power on. refer to bod12 register. 22 bod12 enable bod12 enable at power on. refer to bod12 register. 24:23 bod12 action bod12 action at power on. refer to bod12 register. 25 wdt enable wdt enable at power on. refer to wdt ctrl register. 26 wdt always-on wdt always-on at power on. refer to wdt ctrl register. 30:27 wdt period wdt period at power on. refer to wdt config register. 34:31 wdt window wdt window mode time-out at power on. refer to wdt config register. 38:35 wdt ewoffset wdt early warning interrupt time of fset at power on. refer to wdt ewctrl register. 39 wdt wen wdt timer window mode enable at power on. refer to wdt ctrl register. 47:40 reserved 63:48 lock nvm region lock bits. refer to ?nvmctrl ? non-volatile memory controller? on page 266 .
26 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 10.4 nvm software calibration row mapping the nvm software calibration row contains calibration data that are measured and written during production test. these calibration values should be read by the application software and written back to the corresponding register. the nvm software calibration row can be read at address 0x806020. the nvm software calibration row can not be written. table 10-4. nvm software calibration row mapping bit position name description 2:0 reserved 14:3 adc gaincorr adc gain correction. should be written to gaincorr register. 26:15 adc offsetcorr adc offset correction. should be written to offsetcorr register. 34:27 adc linearity adc linearity calibration. should be written to calib register. 37:35 adc biascal adc bias calibration. should be written to calib register. 63:38 reserved
27 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 11. processor and architecture 11.1 cortex-m0+ processor the atmel ? sam d20 implements the arm ? cortex ? -m0+ processor, which is based on the armv6 architecture and thumb?-2 isa. the cortex m0+ is 100% instruction set compatible with its predecessor, the cortex-m0 processor, and upward compatible with the cortex-m3 and cortex-m4 proces sors. the arm cortex-m0+ implemented is revision r0p1. for more information, refer to www.arm.com . 11.1.1 cortex-m0+ configuration note: 1. all software run in privileged mode only the arm cortex-m0+ processor has two bus interfaces: z single 32-bit amba? 3 ahb-lite? system interface that provides connections to peripherals and all system memory, including flash and ram z single 32-bit i/o port bus interfacing to the port with one-cycle loads and stores 11.1.2 cortex-m0+ peripherals z system control space (scs) z the processor provides debug through registers in the scs. refer to the cortex-m0+ technical reference manual for details. z system timer (systick) z the system timer is a 24-bit timer that extends the functionality of both the processor and the nvic. refer to the cortex-m0+ technical reference manual for details. z nested vectored interrupt controller (nvic) feature configurable option sam d20 configuration interrupts external interrupts 0-32 32 data endianness little-endian or big-endian little-endian systick timer present or absent present number of watchpoint comparators 0, 1, 2 2 number of breakpoint comparators 0, 1, 2, 3, 4 4 halting debug support present or absent present multiplier fast or small fast (single cycle) single-cycle i/o port present or absent present wake-up interrupt controller supported or not supported not supported vector table offset register present or absent present unprivileged/privileged support present or absent absent memory protection unit not present or 8-region not present reset all registers present or absent absent (1) instruction fetch width 16-bit only or mostly 32-bit 32-bit
28 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z external interrupt signals connect to the nvic, and the nv ic prioritizes the interrupts. software can set the priority of each interrupt. the nvic and the cortex-m0+ processor core are closely coupled, providing low latency interrupt processing and efficient processing of late arriving interrupts. refer to ?nested vector interrupt controller? on page 28 and the cortex-m0+ technical reference manual for details. z system control block (scb) z the system control block provides system implementation information, and system control. this includes configuration, control, and reporting of the system exceptions. refer to the cortex-m0+ devices generic user guide for details. 11.1.3 cortex-m0+ address map table 11-1. cortex-m0+ address map 11.1.4 i/o interface 11.1.4.1 overview because accesses to the amba ahb-lite and the single-cycle i/o interface can be made concurrently, the cortex-m0+ processor can fetch the next instructions while accessing the i/os. this enables single-cycle i/o accesses to be sustained for as long as needed. 11.1.4.2 description direct access to port registers. 11.2 nested vector interrupt controller 11.2.1 overview the armv6-m nested vectored interrupt controller (nvic) in t he sam d20 supports 32 interrupt lines with four different priority levels. for more details, refer to the cortex-m0+ technical reference manual ( www.arm.com) . 11.2.2 interrupt line mapping each of the 32 interrupt lines is connected to one peripheral instance, as shown in the table below. each peripheral can have one or more interrupt flags, located in the peripheral?s interrupt flag status and cl ear (intflag) register. the interrupt flag is set when the interrupt condition occurs. each interrupt in the peripheral can be individually enabled by writing a one to the corresponding bit in the peripheral?s in terrupt enable set (intenset) register, and disabled by writing a one to the corresponding bit in the peripheral?s inte rrupt enable clear (intenclr) register. an interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt requests for one peripheral are ored together on system level, generating one interrupt request for each peripheral. an interrupt request will set the corresponding interrupt pending bit in the nvic interrupt pending registers (setpend/clrpend bits in ispr /icpr). for the nvic to activate the interr upt, it must be enabled in the nvic interrupt enable register (setena/clrena bits in iser/icer). the nvic interrupt priority registers ipr0-ipr7 provide a priority field for each interrupt. address peripheral 0xe000e000 system control space (scs) 0xe000e010 system timer (systick) 0xe000e100 nested vectored inte rrupt contro ller (nvic) 0xe000ed00 system control block (scb)
29 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 11.3 high-speed bus matrix 11.3.1 features the high-speed bus matrix includes these features: z symmetric crossbar bus switch implementation z allows concurrent accesses from different masters to different slaves z 32-bit data bus z operation at a one-to-one clock frequency with the bus masters peripheral source nvic line eic nmi ? external interrupt controller non maskable interrupt nmi pm ? power manager 0 sysctrl ? system controller 1 wdt ? watchdog timer 2 rtc ? real time counter 3 eic ? external in terrupt controller 4 nvmctrl ? non-volatile memory controller 5 evsys ? event system 6 sercom0 ? serial communication interface 0 7 sercom1 ? serial communication interface 1 8 sercom2 ? serial communication interface 2 9 sercom3 ? serial communication interface 3 10 sercom4 ? serial communication interface 4 11 sercom5 ? serial communication interface 5 12 tc0 ? timer/counter 0 13 tc1 ? timer/counter 1 14 tc2 ? timer/counter 2 15 tc3 ? timer/counter 3 16 tc4 ? timer/counter 4 17 tc5 ? timer/counter 5 18 tc6 ? timer/counter 6 19 tc7 ? timer/counter 7 20 adc ? analog-to-digital converter 21 ac ? analog comparator 22 dac ? digital-to-analog converter 23 ptc ? peripheral touch controller 24
30 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 11.3.2 configuration cm0+ 0 dsu 1 high-speed bus slaves internal flash 0 ahb-apb bridge a 1 ahb-apb bridge b 2 ahb-apb bridge c 3 internal sram 4 high-speed bus masters
31 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 11.4 ahb-apb bridge the ahb-apb bridge is an ahb slave, providing an inte rface between the high-speed ahb domain and the low-power apb domain. it is used to provide access to the programmable control registers of peripherals (see ?product mapping? on page 23 ). to operate the ahb-apb bridge, the cl ock (clk_hpbx_ahb) must be enabled. see ?pm ? power manager? on page 105 for details. 11.5 pac ? periphera l access controller 11.5.1 overview there is one pac associated with each ahb-apb bridge. t he pac can provide write protection for registers of each peripheral connected on the same bridge. the pac peripheral bus clock (clk_p acx_apb) is enabled by default, and can be enabled and disabled in the power manager. refer to ?pm ? power manager? on page 105 for details. the pac will continue to operate in any sleep mode where the selected clock source is running. write-protection does not apply for debugger access. when the debugger makes an access to a peripheral, write- protection is ignored so that the debugger can update the register. write-protect registers allow the user to disable a select ed peripheral?s write-protection without doing a read-modify-write operation. these registers are mapped into two i/o memory locations, one for clearing and one for setting the register bits. writing a one to a bit in the write protect clear regist er (wpclr) will clear the corresponding bit in both registers (wpclr and wpset) and disable the write-protection for t he corresponding peripheral, while writing a one to a bit in the write protect set (wpset) regi ster will set the corresponding bit in bo th registers (wpclr and wpset) and enable the write-protection for the corresponding peripheral. both regi sters (wpclr and wpset) will return the same value when read. if a peripheral is write-protected, and if a write access is per formed, data will not be written, and the peripheral will retur n an access error (cpu exception). the pac also offers a safety feature for correct program execution, with a cpu exception generated on double write- protection or double unprotection of a peripheral. if a peripheral n is write-protected and a write to one in wpset[n] is detected, the pac returns an error. this can be used to ensure that the application follows the intended program flow by always following a write-protect with an unprotect, and vice versa. however, in applications where a write-protected peripheral is used in several contexts, e.g., interrupts, ca re should be taken so that either the interrupt can not happen while the main application or other interrupt levels manipul ate the write-protection status, or when the interrupt handler needs to unprotect the peripheral, based on the cu rrent protection status, by reading wpset.
32 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 11.5.2 register description atomic 8-, 16- and 32-bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. please refer to ?product mapping? on page 23 for pac locations.
33 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 11.5.2.1 write protect clear name: wpclr offset: 0x00 reset: 0x00000000 property: - z bits 31:7 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 6:1 ? eic, rtc, wdt, gclk, sysctrl, pm: write protect disable 0: write-protection is disabled. 1: write-protection is enabled. writing a zero to these bits has no effect. writing a one to these bits will clear the write protect bits for the corresponding peripherals. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. 11.5.3 write protect set name: wpset offset: 0x04 reset: 0x00000000 bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 accessrrrrrrrr reset00000000 bit151413121110 9 8 accessrrrrrrrr reset00000000 bit76543210 eic rtc wdt gclk sysctrl pm access r r/w r/w r/w r/w r/w r/w r reset00000000
34 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 property: - z bits 31:7 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 6:1 ? eic, rtc, wdt, gclk, sysctrl, pm: write protect enable 0: write-protection is disabled. 1: write-protection is enabled. writing a zero to these bits has no effect. writing a one to these bits will set the write protect bit for the corresponding peripherals. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 15 14 13 12 11 10 9 8 accessrrrrrrrr reset00000000 bit76543210 eic rtc wdt gclk sysctrl pm access r r/w r/w r/w r/w r/w r/w r reset00000000
35 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 11.5.3.1 pac1 register description write protect clear name: wpclr offset: 0x00 reset: 0x00000002 property: - z bits 31:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 3:1 ? port, nvmctrl, dsu: write protect 0: write-protection is disabled. 1: write-protection is enabled. writing a zero to these bits has no effect. writing a one to these bits will clear the write protect bit for the corresponding peripherals. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 accessrrrrrrrr reset00000000 bit151413121110 9 8 accessrrrrrrrr reset00000000 bit76543210 port nvmctrl dsu access r r r r r/w r/w r/w r reset00000010
36 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 write protect set name: wpset offset: 0x04 reset: 0x00000002 property: - z bits 31:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 3:1 ? port, nvmctrl, dsu: write protect 0: write-protection is disabled. 1: write-protection is enabled. writing a zero to these bits has no effect. writing a one to these bits will set the write protect bit for the corresponding peripherals. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 15 14 13 12 11 10 9 8 accessrrrrrrrr reset00000000 bit76543210 port nvmctrl dsu accessrrrrr/wr/wr/wr reset00000010
37 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 11.5.3.2 pac2 register description write protect clear name: wpclr offset: 0x00 reset: 0x00100000 property: - z bits 31:20 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to reset value when this register is written. t hese bits will always return reset value when read. z bits 19:1 ? ptc, dac, ac, adc, tc7, tc6, tc5, tc4, tc3, tc2, tc1, tc0, sercom5, sercom4, sercom3, sercom2, sercom1, sercom0, evsys: write protect 0: write-protection is disabled. 1: write-protection is enabled. writing a zero to these bits has no effect. writing a one to these bits will clear the write protect bit for the corresponding peripherals. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 ptc dac ac adc access r r r r r/w r/w r/w r/w reset00010000 bit151413121110 9 8 tc7tc6tc5tc4tc3tc2tc1tc0 access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 sercom5 sercom4 sercom3 sercom2 sercom1 sercom0 evsys access r/w r/w r/w r/w r/w r/w r/w r reset00000000
38 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 write protect set name: wpset offset: 0x04 reset: 0x00100000 property: - z bits 31:20 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to reset value when this register is written. t hese bits will always return reset value when read. z bits 19:1 ? ptc, dac, ac, adc, tc7, tc6, tc5, tc4, tc3, tc2, tc1, tc0, sercom5, sercom4, sercom3, sercom2, sercom1, sercom 0, evsys: write protect enable 0: write-protection is disabled. 1: write-protection is enabled. writing a zero to these bits has no effect. writing a one to these bits will set the write protect bit for the corresponding peripherals. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 ptc dac ac adc access r r r r r/w r/w r/w r/w reset00010000 bit151413121110 9 8 tc7tc6tc5tc4tc3tc2tc1tc0 access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 sercom5 sercom4 sercom3 sercom2 sercom1 sercom0 evsys access r/w r/w r/w r/w r/w r/w r/w r reset00000000
39 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 12. peripherals configuration overview the following table shows an overview of all the peripherals in the device. the irq line column shows the interrupt mapping, as described in ?nested vector interrupt controller? on page 28 . the ahb and apb clock indexes correspond to the bit in the ahbmask and apbmask (x = a, b or c) registers in the power manager, while the enabled at reset column shows whet her the peripheral clock is enabled at reset (y) or not (n). refer to the power manager ahbmask , apbamask , apbbmask and apbcmask registers for details. the generic clock index column corresponds to the value of the generic clock selection id bits in the generic clock control register (clkctrl.id) in the gener ic clock controller. refer to the gclk clkctrl register description for details. the pac index column corresponds to the bit in the paci (i = 0, 1 or 2) registers, while the prot at reset column shows whether the peripheral is protected at reset (y) or not (n). refer to ?pac ? peripheral access controller? on page 31 for details. the numbers in the events user column correspond to the value of the user multiplexer selection bits in the user multiplexer register (user.user) in the event system. see the user register description and table 23-6 for details. the numbers in the events generator column correspond to the value of the event generator bits in the channel register (channel.evgen) in the event system. see the channel register description and table 23-3 for details. table 12-1. peripherals configuration overview peripheral name base address irq line ahb clock apb clock generic clock pac events index enabled at reset index enabled at reset index index prot at reset user generator hpb0 peripheral bridge a 0x40000000 0 y pac0 0x40000000 0 y pm 0x40000400 0 1 y 1 n sysctrl 0x40000800 1 2 y 0: dfll48m reference 2 n gclk 0x40000c00 3 y 3 n wdt 0x40001000 2 4 y 1 4 n rtc 0x40001400 3 5 y 2 5 n 1: cmp0/alarm0 2: cmp1 3: ovf 4-11: per0-7 eic 0x40001800 nmi, 4 6 y 3 6 n 12-27: extint0-15 hpb1 peripheral bridge b 0x41000000 1 y pac1 0x41000000 0 y dsu 0x41002000 3 y 1 y 1 y nvmctrl 0x41004000 5 4 y 2 y 2 n port 0x41004400 3 y 3 n hpb2 peripheral bridge c 0x42000000 2 y pac2 0x42000000 0 n evsys 0x42000400 6 1 n 4-11: one per channel 1 n sercom0 0x42000800 7 2 n 13: core 12: slow 2 n sercom1 0x42000c00 8 3 n 14: core 12: slow 3 n
40 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 sercom2 0x42001000 9 4 n 15: core 12: slow 4 n sercom3 0x42001400 10 5 n 16: core 12: slow 5 n sercom4 0x42001800 11 6 n 17: core 12: slow 6 n sercom5 0x42001c00 12 7 n 18: core 12: slow 7 n tc0 0x42002000 13 8 n 19 8 n 0: tc 28: ovf 29-30: mc0-1 tc1 0x42002400 14 9 n 19 9 n 1: tc 31: ovf 32-33: mc0-1 tc2 0x42002800 15 10 n 20 10 n 2: tc 34: ovf 35-36: mc0-1 tc3 0x42002c00 16 11 n 20 11 n 3: tc 37: ovf 38-39: mc0-1 tc4 0x42003000 17 12 n 21 12 n 4: tc 40: ovf 41-42: mc0-1 tc5 0x42003400 18 13 n 21 13 n 5: tc 43: ovf 44-45: mc0-1 tc6 0x42003800 19 14 n 22 14 n 6: tc 46: ovf 47-48: mc0-1 tc7 0x42003c00 20 15 n 22 15 n 7: tc 49: ovf 50-51: mc0-1 adc 0x42004000 21 16 y 23 16 n 8: start 9: sync 52: resrdy 53: winmon ac 0x42004400 22 17 n 24: dig 25: ana 17 n 10-11: comp0-1 54-55: comp0-1 56: win0 dac 0x42004800 23 18 n 26 18 n 12: start 57: empty ptc 0x42004c00 24 19 n 27 19 n 13: stconv 58: eoc 59: wcomp table 12-1. peripherals configuration overview peripheral name base address irq line ahb clock apb clock generic clock pac events index enabled at reset index enabled at reset index index prot at reset user generator
41 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13. dsu ? device service unit 13.1 overview the device service unit (dsu) provides a means to detect debugger probes. this enables the arm debug access port (dap) to have control over multiplexed debug pads and cpu reset. the dsu also provides system-level services to debug adapters in an arm debug system. it implements a coresight debug rom that provides device identification a swell as identification of other debug components in the system. hence, it complies with the arm peripheral identification specification. the dsu also provides system services to applications that need memory testing, as required for iec60730 class b compliance, for example. the dsu can be accessed simultaneously by a debugger and the cpu, as it is connected on the high-speed bus matrix. for security reasons, some of the dsu features will be limited or unavailable when the device is protected by the nvmctrl security bit (refer to ?security bit? on page 273 ). 13.2 features z cpu reset extension z debugger probe detection (cold- and hot-plugging) z chip-erase command and status z 32-bit cyclic redundancy check (crc32) of any memory accessible through the bus matrix z arm ? coresight? compliant device identification z two debug communications channels z debug access port security filter z onboard memory built-in self-test (mbist) 13.3 block diagram figure 13-1. dsu bock diagram d su s w c lk co re s i g ht r om dap s e cu rity filte r c rc-32 mbi st c hip eras e r e s et c pu_reset_extens i o n cp u d ap s wdi o nvm c trl hram db g m high-speed high- spee bus matrix matr us m s m s d e b ugger_presen t d e b u g g e r p r o b e interfa ce a hb-a p portmux
42 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.4 signal description refer to ?i/o multiplexing and considerations? on page 15 for details on the pin mapping for this peripheral. 13.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 13.5.1 i/o lines the swclk pin is by default assigned to the dsu module to allow debugger probe detection and the condition to stretch the cpu reset phase. for more information, refer to ?debugger probe detection? on page 43 . the hot-plugging feature depends on the port configuration. if the swclk pin function is changed in the port or if the port_mux is disabled, the hot-plugging feature is disabled until a power-reset or an external reset. 13.5.2 power management the dsu will continue to operate in any sleep mode where the selected source clock is running. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. 13.5.3 clocks the dsu bus clocks (clk_dsu_apb and clk_dsu_ahb) can be enabled and disabled in the power manager. for more information on the clk_dsu_apb and clk_dsu_ahb clock masks, refer to ?pm ? power manager? on page 105 . 13.5.4 interrupts not applicable. 13.5.5 events not applicable. 13.5.6 register access protection all registers with write access are optionally write-protec ted by the peripheral access controller (pac), except the following registers: z debug communication channel 0 register (dcc0) z debug communication channel 1 register (dcc1) write-protection is denoted by the write-protection property in the register description. write-protection does not apply for accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details. 13.5.7 analog connections not applicable. signal name type description reset digital input external reset swclk digital input sw clock swdio digital i/o sw bidirectional data pin
43 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.6 debug operation 13.6.1 principle of operation the dsu provides basic services to allow on-chip debug using the arm debug access port and the arm processor debug resources: z cpu reset extension z debugger probe detection for more details on the arm debug components, refer to the arm debug interface v5architecture specification. 13.6.2 cpu rese t extension ?cpu reset extension? refers to the extension of the reset phase of the cpu core after the external reset is released. this ensures that the cpu is not executing code at startup while a debugger connects to the system. it is detected on a reset release event when swclk is low. at startup, swclk is internally pulled up to avoid false detection of a debugger if swclk is left unconnected. when the cpu is held in the reset extension phase, the cpu reset extension bit (crstext) of the status a regi ster (statusa.crstext) is set. to release the cpu, write a one to statusa.crstext. statusa. crstext will then be set to zero. writing a zero to statusa.crstext has no effect. for security reasons, it is not possible to release the cpu reset extension when the device is protected by the nvmctrl security bit (refer to ?security bit? on page 273 ). trying to do so sets the protection error bit (perr) of the status a register (statusa.perr). figure 13-2. typical cpu reset extension set and clear timing diagram 13.6.3 debugger probe detection 13.6.3.1 cold-plugging cold-plugging is the detection of a debugger when the system is in reset. cold-plugging is detected when the cpu reset extension is requested, as described above. 13.6.3.2 hot-plugging hot-plugging is the detection of a debugger probe when the system is not in reset. hot-plugging is not possible under reset because the detector is reset when por or reset are asserted. hot-plugging is active when a swclk falling edge is detected. the swclk pad is multiplexed with other func tions and the user must ensure that its default function is assigned to the debug system. if the swclk function is c hanged, the hot-plugging feature is disabled until a power- reset or external reset occurs. availability of the hot-pl ugging feature can be read from the hot-plugging enable bit of the status b register (statusb.hpe). dsu crstext clear swclk cpu reset extension cpu_state reset running re s e t
44 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 13-3. hot-plugging detection timing diagram the presence of a debugger probe is detected when either hot- plugging or cold-plugging is detected. once detected, the debugger present bit of the status b register (statusb.d bgpres) is set. for security reasons, hot-plugging is not available when the device is protected by the nvmctrl security bit (refer to ?security bit? on page 273 ). this detection requires that pads are correctly powered. thus, at cold startup, this detection cannot be done until por is released. if the device is protected, cold-plugging is the only way to detect a debugger probe, and so the external reset timing must be longer than the por timing. if external reset is deasserted before por release, the user must retry the procedure above until it gets connected to the device. 13.7 chip-erase chip-erase consists of removing all sensitive information stor ed in the chip and clearing the nvmctrl security bit (refer to ?security bit? on page 273 ). hence, all volatile memories and the flash array (including the eeprom emulation area) will be erased. the flash auxiliary rows, including the user row, will not be erased. when the device is protected, the debugger must reset the device in order to be detected. this ens ures that internal registers are reset after the protected state is removed. the chip-erase operation is triggered by writing a one to the chip-erase bit in the control register (ctrl.ce). this command will be discarded if the dsu is pr otected by the peripheral access controller (pac). once issued, the module clears volatile memories prior to erasing the flash array. to ensure that the chip-erase operation is completed, check the done bit of the status a register (statusa.done). the chip-erase operation depends on clocks and power management features that can be altered by the cpu. for that reason, it is recommended to issue a chip- erase after a cold-plugging procedure to ensure that the device is in a known and safe state. the recommended sequence is as follows: 1. issue the cold-plugging procedure (refer to ?cold-plugging? on page 43 ). the device then: 1. detects the debugger probe 2. holds the cpu in reset 2. issue the chip-erase command by writing a one to ctrl.ce. the device then: 1. clears the system volatile memories 2. erases the whole flash array (including the ee prom emulation area, not including auxiliary rows) 3. erases the lock row, removing the nvmctrl security bit protection 3. check for completion by polling statusa.done (read as one when completed). 4. reset the device to let the nvmctrl update fuses. 13.8 programming programming of the flash or ram memories is available when the device is not protected by the nvmctrl security bit (refer to ?security bit? on page 273 ). swclk hot-plugging cpu_state reset running r eset
45 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 1. at power up, reset is driven low by a debugger. the on-chip regulator holds the system in a por state until the input supply is above the por threshold. the system continues to be held in this static state until the internally regulated supplies have reached a safe operating state. 2. the pm starts, clocks are switched to the slow clock (core clock, system clock, flash clock and any bus clocks that do not have clock gate control). internal resets are maintained due to the external reset. 3. the debugger maintains a low level on swclk. releasing reset results in a debugger cold-plugging procedure. 4. the debugger generates a clock signal on the swclk pin, the debug access port (dap) receives a clock. 5. the cpu remains in reset due to the cold-plugging procedure; meanwhile, the rest of the system is released. 6. a chip-erase is issued to ensure that the flash is fully erased prior to programming. 7. programming is available through the ahb-ap. 8. after operation is completed, the chip can be restarted either by asserting reset , toggling power or writing a one to the status a register cpu reset phase extension bit (statusa.crstext). make sure that the swclk pin is high when releasing reset to prevent extending the cpu reset. 13.9 intellectual pr operty protection intellectual property protection consists of restricting access to internal memories from external tools when the device is protected, and is accomplished by setti ng the nvmctrl security bit (refer to ?security bit? on page 273 ). this protected state can be removed by issuing a chip-erase (refer to ?chip-erase? on page 44 ). when the device is protected, read/write accesses using the ahb-ap are limited to the dsu address range and dsu commands are restricted. the dsu implements a security filter that monitors the ahb transactions generated by the arm ahb-ap inside the dap. if the device is protected, then ahb-ap read/write accesses outside the dsu external address range are discarded, causing an error response that sets the arm ahb-ap sticky erro r bits (refer to the arm debug interface v5 architecture specification on http://www.arm.com ). the dsu is intended to be accessed either: z internally from the cpu, without any limitation, even when the device is protected z externally from a debug adapter, with some restrictions when the device is protected for security reasons, dsu features have limitations when us ed from a debug adapter. to differentiate external accesses from internal ones, the first 0x100 bytes of the dsu register map have been replicated at offset 0x100: z the first 0x100 bytes form the internal address range z the next 0x100 bytes form the external address range when the device is protected, the dap can only issue mem-ap accesses in the dsu address range limited to the 0x100- 0x2000 offset range. the dsu operating registers are located in the 0x00-0xff area and remapped in 0x100-0x1ff to differentiate accesses coming from a debugger and the cpu. if the device is protected and an access is issued in the region 0x100-0x1ff, it is subject to security restrictions. for more information, refer to table .
46 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 some features not activated by apb transactions are not available when the device is protected: 13.10 device identification device identification relies on the arm coresight component identification scheme, which allows the chip to be identified as an atmel device implementing a dsu. the dsu contains identification registers to differentiate the device. 13.10.1 coresight identification a system-level arm coresight rom table is present in the device to identify the vendor and the chip identification method. its address is provided in the mem-ap base regist er inside the arm debug access port. the coresight rom implements a 64-bit conceptual id composed as follows from the pid0 to pid7 coresight rom table registers: figure 13-5. conceptual 64-bit peripheral id figure 13-4. apb memory mapping 0x0000 dsu operating registers internal address range (cannot be accessed from debug tools when the device is protected by the nvmctrl security bit) 0x00fc 0x0100 replicated dsu operating registers external address range (can be accessed from debug tools with some restrictions) 0x01fd empty 0x1000 dsu coresight rom 0x1ffc table 13-1. feature availability under protection features availability when the device is protected cpu reset extension yes debugger cold-plugging yes debugger hot-plugging no
47 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 for more information, refer to the arm debug interface version 5 architecture specification. 13.10.2 dsu chip identification method: the dsu did register identifies the device by implementing the following information: z processor identification z family identification z subfamily identification z device select 13.11 functional description 13.11.1 principle of operation the dsu provides memory services such as crc32 or mbis t that require almost the same interface. hence, the address, length and data registers are shared. they must be configured first; then a command can be issued by writing the control register. when a command is ongoing, other commands are discarded until the current operation is completed. hence, the user must wait for the statusa.done bit to be set prior to issuing another one. 13.11.2 basic operation 13.11.2.1 initialization the module is enabled by enabling its clocks. for more details, refer to ?clocks? on page 42 . the dsu registers can be write-protected. refer to ?pac ? peripheral access controller? on page 31 . 13.11.2.2 operation fr om a debug adapter debug adapters should access the dsu registers in the external address range 0x100 ? 0x2000. if the device is protected by the nvmctrl security bit (refer to ?security bit? on page 273 ), accessing the first 0x100 bytes causes the system to return an error (refer to ?intellectual property protection? on page 45 ). 13.11.2.3 operation from the cpu there are no restrictions when accessing dsu registers from the cpu. however, the user should access dsu registers in the internal address range (0x0 ? 0x100) to avoid external security restrictions (refer to ?intellectual property protection? on page 45 ). table 13-2. conceptual 64-bit pe ripheral id bit descriptions field size description location jep-106 cc code 4 atmel continuation code: 0x0 pid4 jep-106 id code 7 atmel device id: 0x1f pid1+pid2 4kb count 4 indicates that the coresight component is a rom: 0x0 pid4 revand 4 not used; read as 0 pid3 cusmod 4 not used; read as 0 pid3 partnum 12 contains 0xcd0 to indicate that dsu is present pid0+pid1 revision 4 dsu revision (starts at 0x0 and increments by 1 at both major and minor revisions). identifies dsu identifica tion method variants. if 0x0, this indicates that device i dentification can be completed by reading the device identificatio n register (did) pid3
48 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.11.3 32-bit cyclic redundancy check (crc32) the dsu unit provides support for calculating a cyclic redundancy check (crc32) value for a memory area (including flash and ahb ram). when the crc32 command is issued from: z the internal range, the crc32 can be operated at any memory location z the external range, the crc32 operation is restricted; data, addr and length values are forced (see below) the algorithm employed is the industry standard crc 32 algorithm using the generator polynomial 0xedb88320 (reversed representation). 13.11.3.1 starting crc32 calculation crc32 calculation for a memory range is started after writi ng the start address into the address register (addr) and the size of the memory range into the length register (length). both must be word-aligned. the initial value used for the crc32 calculation must be written to the data register. this value will usually be 0xffffffff, but can be, for example, the result of a pr evious crc32 calculation if generating a common crc32 of separate memory blocks. once completed, the calculated crc32 value can be read out of the data register. the read value must be complemented to match standard crc32 implementations or kept non-inverted if used as starting point for subsequent crc32 calculations. if the device is in protected state by the nvmctrl security bit (refer to ?security bit? on page 273 ), it is only possible to calculate the crc32 of the whole flash array. in most case s, this area will be the entire onboard non-volatile memory. the address, length and data registers will be forced to predefined values once the crc32 operation is started, and values written by the user are ignored. this allows the user to verify the contents of a protected device. the actual test is started by writing a one in the 32-bit c yclic redundancy check bit of the control register (ctrl.crc). a running crc32 operation can be canceled by resetting the module (writing a one to ctrl.swrst). 13.11.3.2 interpreting the results the user should monitor the status a register. when the oper ation is completed, statusa.done is set. then the bus error bit of the status a register (statusa.berr) must be read to ensure that no bus error occurred. 13.11.4 debug communication channels the debug communication channels (dcco and dcc1) consist of a pair of registers with associated handshake logic, accessible by both cpu and debugger even if the device is protected by the nvmctrl security bit (refer to ?security bit? on page 273 ). the registers can be used to exchange data between the cpu and the debugger, during run time as well as in debug mode. this enables the user to build a custom debug protocol using only these registers. the dcc0 and dcc1 registers are accessible when the protected state is active. when the device is protected, however, it is not possible to connect a debugger while the cpu is running (statusa.c rstext is not writable and the cpu is held under reset). dirty bits in the status registers indicate whether a new value has been written in dcc0 or dcc1. these bits,dcc0d and dcc1d, are located in the statusb regist ers. they are automatically set on write and cleared on table 13-3. amod bit descriptions when operating crc32 amod[1:0] short name external range restrictions 0 array crc32 is restricted to the full flash array area (eeprom emulation area not included) data forced to 0xffffffff before calculation (no seed) 1 eeprom crc32 of the whole eeprom emulation area data forced to 0xffffffff before calculation (no seed) 2-3 reserved
49 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 read. the dcc0 and dcc1 registers are shared with the onboar d memory testing logic (mbist). accordingly, dcc0 and dcc1 must not be used while performing mbist operations. 13.11.5 testing of onboard memories (mbist) the dsu implements a feature for automatic testing of memo ry also known as mbist. this is primarily intended for production test of onboard memories. mbist cannot be operated from the external address range when the device is protected by the nvmctrl security bit (refer to ?security bit? on page 273 ). if a mbist command is issued when the device is protected, a protection error is reported in the prot ection error bit in the status a register (statusa.perr). 1. algorithm the algorithm used for testing is a type of march algorithm called "march lr". this algorithm is able to detect a wide range of memory defects, while still keeping a linear run time. the algorithm is: 1. write entire memory to 0, in any order. 2. bit for bit read 0, write 1, in descending order. 3. bit for bit read 1, write 0, read 0, write 1, in ascending order. 4. bit for bit read 1, write 0, in ascending order. 5. bit for bit read 0, write 1, read 1, write 0, in ascending order. 6. read 0 from entire memory, in ascending order. the specific implementation used has a run time of o(14n) where n is the number of bits in the ram. the detected faults are: z address decoder faults z stuck-at faults z transition faults z coupling faults z linked coupling faults z stuck-open faults 2. starting mbist to test a memory, you need to write the start address of the memory to the addr.addr bit group, and the size of the memory into the length register. see ?physical memory map? on page 24 to know which memories are avail- able, and which address they are at. for best test coverage, an entire physical memory block should be tested at once. it is possible to test only a sub- set of a memory, but the test coverage will then be somewhat lower. the actual test is started by writing a one to ctrl.m bist. a running mbist operation can be canceled by writing a one to ctrl.swrst. 3. interpreting the results the tester should monitor the statusa register. when the operation is completed, statusa.done is set. there are three different modes: z addr.amod=0: exit-on-error (default) in this mode, the algorithm terminates either when a fault is detected or on successful completion. in both cases, statusa.done is set. if an error was detected, statusa.fail will be set. user then can read the data and addr registers to locate the fault. refer to ?locating errors? on page 49 . z addr.amod=1: pause-on-error in this mode, the mbist algorithm is paused when an error is detected. in such a situation, only statusa.fail is asserted. the state machine waits for user to clear stat usa.fail by writing a one in statusa.fail to resume. prior to resuming, user can read the data and addr registers to locate the fault. refer to ?locating errors? on page 49 . 4. locating errors if the test stops with statusa.fail set, one or more bits failed the test. the test stops at the first detected error. the position of the failing bit can be found by reading the following registers:
50 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z addr: address of the word containing the failing bit. z data: contains data to identify which bit failed, and during which phase of the test it failed. the data register will in this case contains the following bit groups: table 13-4. data bits description when mbist operation returns an error z bit_index: contains the bit number of the failing bit z phase: indicates which phase of the test failed and the cause of the error. see table 13-5 on page 50 . 13.11.6 system services availability when accessed externally external access: access performed in t he dsu address offset 0x200-0x1fff range. internal access: access performed in the dsu address offset 0x0-0x100 range. bit3130292827262524 bit2322212019181716 bit151413121110 9 8 phase bit76543210 bit_index table 13-5. mbist operation phases phase test actions 0 write all bits to zero. this phase cannot fail. 1 read 0, write 1, increment address 2 read 1, write 0 3 read 0, write 1, decrement address 4 read 1, write 0, decrement address 5 read 0, write 1 6 read 1, write 0, decrement address 7 read all zeros. bit_index is not used
51 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 13-6. available features when operated from the external address range features availability from the external address range chip-erase command and status yes crc32 yes, only full array or full eeprom coresight compliant de vice identification yes debug communication channels yes testing of onboard memories (mbist) yes statusa.crstext clearing no (statusa.perr is set when attempting to do so)
52 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.12 register summary table 13-7. register summary offset name bit pos 0x0000 ctrl 7:0 ce mbist crc swrst 0x0001 statusa 7:0 perr fail berr crstext done 0x0002 statusb 7:0 hpe dccd1 dccd0 dbgpres prot 0x0003 reserved 0x0004 addr 7:0 addr[5:0] 0x0005 15:8 addr[13:6] 0x0006 23:16 addr[21:14] 0x0007 31:24 addr[29:22] 0x0008 length 7:0 length[5:0] 0x0009 15:8 length[13:6] 0x000a 23:16 length[21:14] 0x000b 31:24 length[29:22] 0x000c data 7:0 data[7:0] 0x000d 15:8 data[15:8] 0x000e 23:16 data[23:16] 0x000f 31:24 data[31:24] 0x0010 dcc0 7:0 data[7:0] 0x0011 15:8 data[15:8] 0x0012 23:16 data[23:16] 0x0013 31:24 data[31:24] 0x0014 dcc1 7:0 data[7:0] 0x0015 15:8 data[15:8] 0x0016 23:16 data[23:16] 0x0017 31:24 data[31:24] 0x0018 did 7:0 devsel[7:0] 0x0019 15:8 die[3:0] revision[3:0] 0x001a 23:16 subfamily[7:0] 0x001c 31:24 processor[3:0] family[3:0] 0x001d reserved ... ... 0x00ff reserved 0x0100- 0x01ff external address range: replicates the 0x00:0x1c address range, gives access to the same resources but with security restrictions when the device is protected. this address range is the only one accessible externally (using the arm dap) when the device is protected.
53 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 0x1000 entry0 7:0 fmt epres 0x1001 15:8 addoff[3:0] 0x1002 23:16 addoff[11:4] 0x1003 31:24 addoff[19:12] 0x1004 entry1 7:0 fmt epres 0x1005 15:8 addoff[3:0] 0x1006 23:16 addoff[11:4] 0x1007 31:24 addoff[19:12] 0x1008 end 7:0 end[7:0] 0x1009 15:8 end[15:8] 0x100a 23:16 end[23:16] 0x100b 31:24 end[31:24] 0x1fcc memtype 7:0 smemp 0x1fcd 15:8 0x1fce 23:16 0x1fcf 31:24 0x1fd0 pid4 7:0 fkbc[3:0] jepcc[3:0] 0x1fd1 15:8 0x1fd2 23:16 0x1fd3 31:24 0x1fd4 reserved ? ? 0x1fdf reserved 0x1fe0 pid0 7:0 partnbl[7:0] 0x1fe1 15:8 0x1fe2 23:16 0x1fe3 31:24 0x1fe4 pid1 7:0 jepidcl[3:0] partnbh[3:0] 0x1fe5 15:8 0x1fe6 23:16 0x1fe7 31:24 0x1fe8 pid2 7:0 revision[3:0] jepu jepidch[2:0] 0x1fe9 15:8 0x1fea 23:16 0x1feb 31:24 0x1fec pid3 7:0 revand[3:0] cusmod[3:0] 0x1fed 15:8 0x1fee 23:16 0x1fef 31:24
54 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 0x1ff0 cid0 7:0 preambleb0[7:0] 0x1ff1 15:8 0x1ff2 23:16 0x1ff3 31:24 0x1ff4 cid1 7:0 cclass[3:0] preamble[3:0] 0x1ff5 15:8 0x1ff6 23:16 0x1ff7 31:24 0x1ff8 cid2 7:0 preambleb2[7:0] 0x1ff9 15:8 0x1ffa 23:16 0x1ffb 31:24 0x1ffc cid3 7:0 preambleb3[7:0] 0x1ffd 15:8 0x1ffe 23:16 0x1fff 31:24
55 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write protection is denoted by the write-protected property in each individual register description. please refer to ?register access protection? on page 42 for details.
56 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.1 control name: ctrl offset: 0x0000 reset: 0x00 property: write-protected z bits 7:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 4 ? ce: chip-erase writing a zero to this bit has no effect. writing a one to this bit starts the chip-erase operation. z bit 3 ? mbist: memory built-in self-test writing a zero to this bit has no effect. writing a one to this bit starts the memory bist algorithm. z bit 2 ? crc: 32-bit cyclic redundancy check writing a zero to this bit has no effect. writing a one to this bit starts the cyclic redundancy check algorithm. z bit 1 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. z bit 0 ? swrst: software reset writing a zero to this bit has no effect. writing a one to this bit resets the module. bit 76543210 ce mbist crc swrst access r r r w w w r w reset00000000
57 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.2 status a name: statusa offset: 0x0001 reset: 0x00 property: write-protected z bits 7:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 4 ? perr: protection error writing a zero to this bit has no effect. writing a one to this bit clears the protection error bit. this bit is set when a command that is not allowed in protected state is issued. z bit 3 ? fail: failure writing a zero to this bit has no effect. writing a one to this bit clears the failure bit. this bit is set when a dsu operation failure is detected. z bit 2 ? berr: bus error writing a zero to this bit has no effect. writing a one to this bit clears the bus error bit. this bit is set when a bus error is detected. z bit 1 ? crstext: cpu reset phase extension writing a zero to this bit has no effect. writing a one to this bit clears the cpu reset phase extension bit. this bit is set when a debug adapter cold-plugging is detected, which extends the cpu reset phase. z bit 0 ? done: done writing a zero to this bit has no effect. writing a one to this bit clears the done bit. this bit is set when a dsu operation is completed. bit 76543210 perr fail berr crstext done access r r r r/w r/w r/w r/w r/w reset00000000
58 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.3 status b name: statusb offset: 0x0002 reset: 0x1x property: write-protected z bits 7:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 4 ? hpe: hot-plugging enable writing a zero to this bit has no effect. writing a one to this bit has no effect. this bit is set when hot-plugging is enabled. this bit is cleared when hot-plugging is disabled. this is the case when the swclk function is changed. only a power-reset or a external reset can set it again. z bits 3:2 ? dccdx [x=1..0]: debu g communication channel x dirty writing a zero to this bit has no effect. writing a one to this bit has no effect. this bit is set when dccx is written. this bit is cleared when dccx is read. z bit 1 ? dbgpres: debugger present writing a zero to this bit has no effect. writing a one to this bit has no effect. this bit is set when a debugger probe is detected. this bit is never cleared. z bit 0 ? prot: protected writing a zero to this bit has no effect. writing a one to this bit has no effect. this bit is set at powerup when the device is protected. this bit is never cleared. bit 76543210 hpe dccd1 dccd0 dbgpres prot accessrrrrrrrr reset000100xx
59 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.4 address name: addr offset: 0x0004 reset: 0x00000000 property: write-protected z bits 31:2 ? addr[29:0]: address initial word start address needed for memory operations. z bits 1:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. bit 3130292827262524 addr[29:22] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 addr[21:14] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 addr[13:6] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 76543210 addr[5:0] access r/w r/w r/w r/w r/w r/w r r reset00000000
60 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.5 length name: length offset: 0x0008 reset: 0x00000000 property: write-protected z bits 31:2 ? length[29:0]: length length in words needed for memory operations. z bits 1:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. bit 3130292827262524 length[29:22] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 length[21:14] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 length[13:6] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 76543210 length[5:0] access r/w r/w r/w r/w r/w r/w r r reset00000000
61 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.6 data name: data offset: 0x000c reset: 0x00000000 property: write-protected z bits 31:0 ? data[31:0]: data memory operation initial value or result value. bit 3130292827262524 data[31:24] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 data[23:16] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 data[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 76543210 data[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
62 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.7 debug communication channel n name: dccn offset: 0x0010+n*0x4 [n=0..1] reset: 0x00000000 property: - z bits 31:0 ? data[31:0]: data data register. bit 3130292827262524 data[31:24] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 data[23:16] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 data[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 76543210 data[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
63 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.8 device identification name: did offset: 0x0018 reset: 0x1000xxxx property: write-protected z bits 31:28 ? processor[3:0]: processor z bits 27:24 ? family[3:0]: family bit 3130292827262524 processor[3:0] family[3:0] accessrrrrrrrr reset00000000 bit 2322212019181716 subfamily[7:0] accessrrrrrrrr reset00000000 bit 151413121110 9 8 accessrrrrrrrr resetxxxxxxxx bit 76543210 devsel[7:0] accessrrrrrrrr resetxxxxxxxx id description 0x0 reserved 0x1 cortex-m0+ 0x2-0xf reserved id description 0x0 general purpose 0x1-0xf reserved
64 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bits 23:16 ? subfamily[7:0]: sub-family z bits 15:8 ? reserved these bits are unused and reserved for future use. z bits 7:0 ? devsel[7:0]: device select the value of devsel is related to the pin count and flash memory density. refer to the ?ordering information sam d20? on page 4 for details, and table 13-8 . id description 0x00 baseline 0x01-0xff reserved table 13-8. devsel select devsel flash ram pincount 0x0 256kb 32kb 64 0x1 128kb 16kb 64 0x2 64kb 8kb 64 0x3 32kb 4kb 64 0x4 16kb 2kb 64 0x5 256kb 32kb 48 0x6 128kb 16kb 48 0x7 64kb 8kb 48 0x8 32kb 4kb 48 0x9 16kb 2kb 48 0xa reserved 0xb 128kb 16kb 32 0xc 64kb 8kb 32 0xd 32kb 4kb 32 0xe 16kb 2kb 32 0xf-0xff reserved
65 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.9 coresight rom table entry n name: entryn offset: 0x1000+n*0x4 [n=0..1] reset: 0xxxxxx00x property: write-protected z bits 31:12 ? addoff[19:0]: address offset the base address of the component, relative to the base address of this rom table. z bits 11:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? fmt: format always read as one, indicates a 32-bit rom table. z bit 0 ? epres: entry present this bit indicates whether an entry is present at this location in the rom table. this bit is set at powerup if the device is not pr otected indicating that the entry is not present. this bit is cleared at powerup if the device is not protected indicating that the entry is present. bit 3130292827262524 addoff[19:12] accessrrrrrrrr resetxxxxxxxx bit 2322212019181716 addoff[11:4] accessrrrrrrrr resetxxxxxxxx bit 151413121110 9 8 addoff[3:0] accessrrrrrrrr resetxxxx0000 bit 76543210 fmt epres accessrrrrrrrr reset0000001x
66 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.10coresight rom table end name: end offset: 0x1008 reset: 0x00000000 property: - z bits 31:0 ? end[31:0]: end marker indicates the end of the coresight rom table entries. bit 3130292827262524 end[31:24] accessrrrrrrrr reset00000000 bit 2322212019181716 end[23:16] accessrrrrrrrr reset00000000 bit 151413121110 9 8 end[15:8] accessrrrrrrrr reset00000000 bit 76543210 end[7:0] accessrrrrrrrr reset00000000
67 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.11coresight rom table memory type name: memtype offset: 0x1fcc reset: 0x0000000x property: - z bits 31:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? smemp: system memory present this bit indicates whether system memory is present on the bus that connects to the rom table. this bit is set at powerup if the device is not protected indicating that the system memory is accessible from a debug adapter. this bit is cleared at powerup if the device is protected i ndicating that the system memory is not accessible from a debug adapter. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 accessrrrrrrrr reset00000000 bit 76543210 smemp accessrrrrrrrr reset0000000x
68 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.12peripheral identification 4 name: pid4 offset: 0x1fd0 reset: 0x00000000 property: - z bits 31:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 7:4 ? fkbc[3:0]: 4kb count these bits will always return zero when read, indi cating that this debug component occupies one 4kb block. z bits 3:0 ? jepcc[3:0]: jep-106 continuation code these bits will always return zero when read, indicating a atmel device. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 accessrrrrrrrr reset00000000 bit 76543210 fkbc[3:0] jepcc[3:0] accessrrrrrrrr reset00000000
69 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.13peripheral identification 0 name: pid0 offset: 0x1fe0 reset: 0x000000d0 property: - z bits 31:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 7:0 ? partnbl[7:0]: part number low these bits will always return 0xd0 when read, indi cating that this device implements a dsu module instance. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 accessrrrrrrrr reset00000000 bit 76543210 partnbl[7:0] accessrrrrrrrr reset11010000
70 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.14peripheral identification 1 name: pid1 offset: 0x1fe4 reset: 0x000000fc property: - z bits 31:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 7:4 ? jepidcl[3:0]: low part of the jep-106 identity code these bits will always return 0xf when read, indica ting a atmel device (atmel jep-106 identity code is 0x1f). z bits 3:0 ? partnbh[3:0]: part number high these bits will always return 0xc when read, indica ting that this device implements a dsu module instance. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 accessrrrrrrrr reset00000000 bit 76543210 jepidcl[3:0] partnbh[3:0] accessrrrrrrrr reset11111100
71 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.15peripheral identification 2 name: pid2 offset: 0x1fe8 reset: 0x00000009 property: - z bits 31:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 7:4 ? revision[3:0]: revision number revision of the peripheral. starts at 0x0 and increments by one at both major and minor revisions. z bit 3 ? jepu: jep-106 identity code is used this bit will always return one when read, indicating that jep-106 code is used. z bits 2:0 ? jepidch[2:0]: jep-106 identity code high these bits will always return 0x1 when read, indicating a atmel device (atmel jep-106 identity code is 0x1f). bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 accessrrrrrrrr reset00000000 bit 76543210 revision[3:0] jepu jepidch[2:0] accessrrrrrrrr reset00001001
72 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.16peripheral identification 3 name: pid3 offset: 0x1fec reset: 0x00000000 property: - z bits 31:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 7:4 ? revand[3:0]: revision number these bits will always return 0x0 when read. z bits 3:0 ? cusmod[3:0]: arm cusmod these bits will always return 0x0 when read. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 accessrrrrrrrr reset00000000 bit 76543210 revand[3:0] cusmod[3:0] accessrrrrrrrr reset00000000
73 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.17component identification 0 name: cid0 offset: 0x1ff0 reset: 0x0000000d property: - z bits 31:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 7:0 ? preambleb0[7:0]: preamble byte 0 these bits will always return 0xd when read. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 accessrrrrrrrr reset00000000 bit 76543210 preambleb0[7:0] accessrrrrrrrr reset00001101
74 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.18component identification 1 name: cid1 offset: 0x1ff4 reset: 0x00000010 property: - z bits 31:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 7:4 ? cclass[3:0]: component class these bits will always return 0x1 when read indicating t hat this arm coresight component is rom table (refer to the arm debug interface v5 architecture specification at http://www.arm.com ). z bits 3:0 ? preamble[3:0]: preamble these bits will always return 0x0 when read. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 accessrrrrrrrr reset00000000 bit 76543210 cclass[3:0] preamble[3:0] accessrrrrrrrr reset00010000
75 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.19component identification 2 name: cid2 offset: 0x1ff8 reset: 0x00000005 property: - z bits 31:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 7:0 ? preambleb2[7:0]: preamble byte 2 these bits will always return 0x05 when read. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 accessrrrrrrrr reset00000000 bit 76543210 preambleb2[7:0] accessrrrrrrrr reset00000101
76 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13.13.20component identification 3 name: cid3 offset: 0x1ffc reset: 0x000000b1 property: - z bits 31:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 7:0 ? preambleb3[7:0]: preamble byte 3 these bits will always return 0xb1 when read. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 accessrrrrrrrr reset00000000 bit 76543210 preambleb3[7:0] accessrrrrrrrr reset10110001
77 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 14. clock system this chapter only aims to summarize the clock distributi on and terminology in the samd20 device. it will not explain every detail of its configuration. for in-depth documentation, see the referenced module chapters. 14.1 clock distribution figure 14-1. clock distribution the clock system on the samd20 consists of: z clock sources , controlled by sysctrl z a clock source is the base clock signal used in the system. example clock sources are the internal 8mhz oscillator (osc8m), external crystal oscillator (xosc) and the digital frequency locked loop (dfll48m). z generic clock controller (gclk) which controls the clock distribution system, made up of: z generic clock generators : a programmable prescaler, that can use any of the system clock sources as its source clock. the generic clock generator 0, also called gclkmain, is the clock feeding the power manager used to generate synchronous clocks. z generic clocks : typically the clock input of a peripheral on the system. the generic clocks, through the generic clock multiplexer, can use any of the generic clock generators as its clock source. multiple instances of a peripheral will typically have a separate generic clock for each in stance. the dfll48m clock input (when multiplying another clock source) is generic clock 0. z power manager (pm) z the pm controls synchronous clocks on the system. this includes the cpu, bus clocks (apb, ahb) as well as the synchronous (to the cpu) user interfaces of the peripherals. it contains clock masks that can turn on/off the user interface of a peripheral as well as prescalers for the cpu and bus clocks. figure 14-2 shows an example where sercom0 is clocked by the dfll48m in open loop mode. the dfll48m is enabled, the generic clock generator 1 uses the dfll48m as its clock source, and the generic clock 13, also called gclk_sercom0_core, that is connected to sercom0 uses generator 1 as its source. the sercom0 interface, clocked by clk_sercom0_apb, has been unmasked in the apbc mask register in the pm. gc lk g enerator 0 s y sc trl gclk gc lk g enerator 1 gc lk g enerator x gclk multi p lexer 0 ( dfll48m reference ) gc lk multiplexer 1 gclk multiplexer y p er i p h era l z peripheral 0 sy ncronous c lock c ontroller pm a hb / apb sy stem c lock s gc lkmai n osc 8m osc 32k osculp32k xosc32k dfll48m xosc g eneric c locks
78 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 14-2. example of sercom clock 14.2 synchronous and asynchronous clocks as the cpu and the peripherals can be clocked from different clock sources, possibly with widely different clock speeds, some peripheral accesses by the cpu needs to be synchronized between the different clock domains. in these cases the peripheral includes a syncbusy status flag that can be used to check if a sync operation is in progress. as the nature of the synchronization might vary between different peripheral s, detailed description for each peripheral can be found in the sub-chapter ?synchronization? for eac h peripheral where this is necessary. in the datasheet references to synchronous clocks are referr ing to the cpu and bus clocks, while asynchronous clocks are clock generated by generic clocks. 14.3 register synchronization 14.3.1 overview all peripherals are composed of one digital bus interface, wh ich is connected to the apb or ahb bus and clocked using a corresponding synchronous clock, and one core clock, which is clocked using a generic clock. access between these clock domains must be synchronized. as this mechanism is implemented in hardware the synchronization process takes place even if the different clocks domains are clocked from the same source and on the same frequency. all registers in the bus interface are accessible without synchronization. all core registers in the generic clock domain must be synchronized when written. some core registers must be synchronized when read. registers that need synchronization has this denoted in each individual register description. two properties are used: write-synchronization and read- synchronization. a common synchronizer is used for all registers in one peripheral, as shown in figure 14-3 . therefore, only one register per peripheral can be synchronized at a time. sysctrl dfll48m g eneric c lock g enerator 1 g eneric c lock multiplexer 13 sercom 0 syncronous clock controller pm clk_sercom0_apb gclk_sercom0_core gclk
79 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 14-3. synchronization 14.3.2 write-sy nchronization the write-synchronization is triggered by a write to any generic clock core register. the synchronization busy bit in the status register (status.syncbusy) will be set when the write-synchronization starts and cleared when the write- synchronization is complete. refer to ref for details on the synchronization delay. when the write-synchronization is ongoing (status.syncbusy is one), any of the following actions will cause the peripheral bus to stall until the synchronization is complete: z writing a generic clock core register z reading a read-synchronized core register z reading the register that is being written (and thus triggered the synchronization) core registers without read-synchronization will remain st atic once they have been written and synchronized, and can be read while the synchronization is ongoing without causing the per ipheral bus to stall. apb registers can also be read while the synchronization is ongoing without causing the peripheral bus to stall. non sync'd reg intflag status readreq write-sync'd reg write-sync'd reg r/w-sync'd reg synchronizer sync syncbusy synchronous domain (clk_apb) asynchronous domain (generic clock) peripheral bus
80 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 14.3.3 read-synchronization reading a read-synchronized core register will cause the peripheral bus to stall immediately until the read- synchronization is complete. status.syncbusy will not be set. refer to ref for details on the synchronization delay. note that reading a read-synchronized core register whil e status.syncbusy is one will cause the peripheral bus to stall twice; first because of the ongoing synchronization, and then again because reading a read-synchronized core register will cause the peripheral bus to stall immediately. 14.3.4 completion of synchronization the user can either poll status.syncbusy or use the sync hronisation ready interrupt (if available) to check when the synchronization is complete. it is also possible to perform the next read/write operation and wait, as this next operation will be started once the previous write/read operation is synchronized and/or complete. 14.3.5 read request the read request functionality is only available to per ipherals that have the read request register (readreq) implemented. refer to the register description of individual peripheral chapters for details. to avoid forcing the peripheral bus to stall when reading r ead-synchronized core registers, the read request mechanism can be used. 14.3.5.1 basic read request writing a one to the read request bit in the read request register (readreq.rreq) will request read- synchronization of the register specified in t he address bits in rea dreq (readreq.addr) and set status.syncbusy. when read-synchr onization is complete, status.s yncbusy is cleared. the read- synchronized value is then available for reading without delay until readreq.rreq is written to one again. the address to use is the offset to the peripherals base address of the register that should be synchronized. hjelp! 14.3.5.2 continuous read request writing a one to the read continuously bit in re adreq (readreq.rcont) will force continuous read- synchronization of the register specified in readreq.addr . the latest value is always available for reading without stalling the bus, as the synchronization mechanism is continuously synchronizing the given value. syncbusy is set for the first synchronization, but not for the subsequent synchronizations. if another synchronization is attempted, i.e. by executing a write-operation of a write-syn chronized register, the read request will be stopped, and will have to be manually restarted. note that continuous read-synchronization is paused in sleep modes where the generic clock is not running. this means that a new read request is required if the value is needed immediately after exiting sleep. 14.3.6 enable write-synchronization writing to the enable bit in the control register (ctr l.enable) will also trigger write-synchronization and set status.syncbusy. ctrl.enabl e will read its new value immediately af ter being written. the synchronisation ready interrupt (if available) cannot be used for enable write-synchronization. when the enable write-synchronization is o ngoing (status.syncbusy is one), attemp t to do any of the following will cause the peripheral bus to stall until the enable synchronization is complete: z writing a core register z writing an apb register z reading a read-synchronized core register apb registers can be read while the enable write-synchronizati on is ongoing without causing the peripheral bus to stall. 14.3.7 software reset write-synchronization writing a one to the software reset bit in ctrl (ctrl.swrst) will also trigger write-synchronization and set status.syncbusy. when writing a one to the ctrl.swrst bit it will immediately read as one. ctrl.swrst and
81 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 status.syncbusy will be cleared by hardware when the peripheral has been reset. writing a zero to the ctrl.swrst bit has no effect. the synchronisation ready in terrupt (if available) cannot be used for software reset write-synchronization. when the software reset is in progress (status.syncbu sy and ctrl.swrst are one), attempt to do any of the following will cause the peripheral bus to stall until the software reset synchronization and the reset is complete: z writing a core register z writing an apb register z reading a read-synchronized register apb registers can be read while the software reset is being write-synchronized without causing the peripheral bus to stall. 14.3.8 synchronization delay the synchronization will delay the write or read a ccess duration by a delay d, given by the equation: where is the period of the generic clock and is the period of the peripheral bus clock. a normal peripheral bus register access duration is . 14.4 enabling a peripheral to enable a peripheral clocked by a generic clock, the following parts of the system needs to be configured: z a running clock source. z a clock from the generic clock generator must be configured to use one of the running clock sources, and the generator must be enabled. z the generic clock, through the generic clock multiplexer, that connects to the peripheral needs to be configured with a running clock from the generic clock generator, and the generic clock must be enabled. z the user interface of the peripheral needs to be unmasked in the pm. if this is not done the peripheral registers will read as all 0?s and any writes to the peripheral will be discarded. 14.5 on-demand, clock requests figure 14-4. clock request routing all the clock sources in the system can be run in an on-demand mode, where the clock source is in a stopped state when no peripherals are requesting the clock source. clock requests propagate from the peripheral, via the gclk, to the clock source. if one or more peripheral is using a clock source, the clock source will be started/kept running. as soon as the clock source is no longer needed and no peripheral have an active request the clock source will be stopped until requested again. for the clock request to reach the clock s ource, the peripheral, the generic clock and the clock from the generic clock generator in-between must be enabled. the time taken from a clock request being asserted to the clock source being ready is dependent on the clock source startup time , clock source frequency as well as the divider used in the generic clock generator. the total startup time from a cl ock request to the clock is available for the peripheral is: delay_start_max = clock source startup time + 2 * cl ock source periods + 2 * divided clock source periods 5 p gclk ? 2 p apb ? + d 6 p gclk ? 3 p apb ? + << p gclk p apb 2 p apb ? dfll48m g eneric c lock g enerator clock request g eneric c lock m ulti p lexer clock request p er iph era l clock request enable runstdby ondemand clken runstdby enable runstdby genen
82 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 delay_start_min = clock source startup time + 1 * clock source period + 1 * divided clock source period the delay for shutting down the clock source when there is no longer an active request is: delay_stop_min = 1 * divided clock source period + 1 * clock source period delay_stop_max = 2 * divided clock source periods + 2 * clock source periods the on-demand principle can be disabled individually for each clock source by clearing the ondemand bit located in each clock source controller. the clock is always running whatever is the clock request. this has the effect to remove the clock source startup time at the cost of the power consumption. in standby mode, the clock request mechanism is still worki ng if the modules are configured to run in standby mode (runstdby bit). 14.6 power consumption vs speed due to the nature of the asynchronous clocking of the peripher als there are some considerations that needs to be taken if either targeting a low-power or a fast-acting system. if cl ocking a peripheral with a very low clock, the active power consumption of the peripheral will be lower. at the same time the synchronization to the synchronous (cpu) clock domain is dependent on the peripheral clock speed, and will be longer with a slower peripheral clock; giving lower response time and more time waiting for the synchronization to complete. 14.7 clocks after reset on any reset the synchronous clocks start to their initial state: z osc8m is enabled and divided by 8 z gclkmain uses osc8m as source z cpu and bus clocks are undivided on a power reset the gclk starts to their initial state: z all generic clock generators disabled except: z the generator 0 (gclkmain) using osc8m as source, with no division z the generator 2 using osculp32k as source, with no division z all generic clocks disabled except: z the wdt generic clock using the generator 2 as source on a user reset the gclk starts to their initial state, except for: z generic clocks that are write-locked (wrtlock is written to one prior to reset or the wdt generic clock if the wdt always-on at power on bit set in the nvm user row) z the generic clock dedicated to the rtc if the rtc generic clock is enabled on any reset the clock sources are reset to their initial state except the 32khz clock sources which are reset only by a power reset.
83 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 15. gclk ? generic clock controller 15.1 overview several peripherals may require specific clock frequencies to operate correctly. the gclk provides a number of generic clock generators that can provide a wide range of clock frequencies. the generic clock generators can be set to use different external and internal clock sources. the clock in each generic clock generator can be divided down. the outputs from the generic clock generators are used as clock sources for the generic clock multiplexers, which select one of the sources to generate a generic clock (gclk_periph), as shown in figure 15-2 . the number of generic clocks, m, depends on how many peripherals the device has. 15.2 features z provides a user-defined number (max 64) of generic clocks z wide frequency range 15.3 block diagram the gclk can be seen in the clocking diagram, which is shown in figure 15-1 . figure 15-1. device clocking diagram the gclk block diagram is shown in figure 15-2 . g clk _ i o g eneric clock generato r osc8m osc3 2k oscu lp 3 2k xosc 32 k s ysctrl c lock d ivider & masker c loc k g at e g eneric c lock multiplexe r gc lk_perip h p eripheral s g eneri c c l oc k co ntr o lle r pm gc lkmai n d fll4 8 m xosc
84 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 15-2. generic clock controller block diagram 15.4 signal description please refer to ?i/o multiplexing and considerations? on page 15 for details on the pin mapping for this peripheral. one signal can be mapped on several pins. 15.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 15.5.1 i/o lines using the gclk?s i/o lines requires the i/o pins to be configured. refer to ?port? on page 289 for details. 15.5.2 power management the gclk can operate in all sleep modes, if required. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. 15.5.3 clocks the gclk bus clock (clk_gclk_apb) can be enabled and disabled in the power manager, and the default state of clk_gclk_apb can be found in the peripheral clock masking section in ?pm ? power manager? on page 105 . 15.5.4 interrupts not applicable. generic clock generator 0 gc lk_i o [0] ( i/o input) c lock d ivider & maske r c lock s ources gclkgen [ 0 ] gc lk_i o [1] ( i/o input ) gc lk g en[1] g clk _ io [ n ] ( i /o input ) gc lk g en[n] clock g at e g eneric c lock multiplexer 0 gclk _ periph [ 0 ] clock g at e g eneric c lock multiplexer 1 c lock g at e g eneric clock multi p lexer m gc lk g en[n:0] gc lkmai n gc lk_i o [1 ] ( i /o output ) gc lk_i o [0 ] (i/o output ) gclk _ io [ n ] ( i /o output ) g eneric c lock g enerator 1 c lock divider & maske r g eneric c lock g enerator n c lock d ivider & m as k er gclk_periph[1] gclk_periph[m] ] signal name type description gclk_io[n..0] digital i/o source clock when input generic clock when output
85 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 15.5.5 events not applicable. 15.5.6 debug operation not applicable. 15.5.7 register access protection all registers with write-access are optionally write-pr otected by the peripheral access controller (pac). write-protection is denoted by the write-protection property in the register description. when the cpu is halted in debug mode or the cpu reset is extended, all write-protection is automatically disabled. write-protection does not apply for accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details. 15.5.8 analog connections not applicable. 15.6 functional description 15.6.1 principle of operation the gclk module is comprised of eight generic clock generators sourcing m generic clock multiplexers. a clock source selected as input to one of the generic clock generators can be used directly, or it can be prescaled in the generic clock generator before the generator out put is used as input to one or more of the generic clock multiplexers . a generic clock multiplexer provides a generic clock to the peripherals (gclk_peripheral). a generic clock can act as the clock to one or several of the peripherals. 15.6.2 basic operation 15.6.2.1 initialization before a generic clock is enabled, the clock source of its generic clock generator should be enabled. the generic clock must be configured as outlined by the following steps: 1. the generic clock generator division factor must be set by performing a single 32-bit write to the generic clock generator division register (gendiv): z the generic clock generator that will be selected as the source of the generic clock must be written to the id bit group (gendiv.id) z the division factor must be written to the div bit group (gendiv.div) 2. the generic clock generator must be enabled by performing a single 32-bit write to the generic clock generator control register (genctrl): z the generic clock generator that will be selected as the source of the generic clock must be written to the id bit group (genctrl.id) z the generic clock generator must be enabled by writing a one to the genen bit (genctrl.genen) 3. the generic clock must be configured by performing a singl e 16-bit write to the generic clock control register (clkctrl): z the generic clock that will be configured must be written to the id bit group (clkctrl.id) z the generic clock generator used as the source of the the generic clock must be written to the gen bit group (clkctrl.gen). 15.6.2.2 enabling, disabling and resetting the gclk module has no enable/disable bit to enable or disable the whole module.
86 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 the gclk is reset by writing a one to the software reset bit in the control register (ctrl.swrst). all registers in the gclk will be reset to their initial state except for generic clocks and associated generators that have their write lock bit written to one. refer to ?configuration lock? on page 88 for details. 15.6.2.3 generic clock generator each generic clock generator (gclkgen) can be set to r un from one of eight different clock sources except gclkgen[1] which can be set to run from one of seven sour ces. gclkgen[1] can act as source to the other generic clock generators but can not act as source to itself. each generic clock generator gclkgen[x] can be connected to one specific gclk_io[x] pin. the gclk_io[x] can be set to act as source to gclkgen[x] or gclk_io[x] can be set up to output the clock generated by gclkgen[x]. the selected source (gclkgensrc see figure 15-3 ) can optionally be divided. each generic clock generator can be independently enabled and disabled. each gclkgen clock can then be used as a clock source for the generic clock multiplexers. each generic clock is allocated to one or several peripherals. gclkgen[0], is used as gclkmain for the synchronous clock controller inside the power manager. refer to ?pm ? power manager? on page 105 for details on the synchronous clock generation. figure 15-3. generic clock generator 15.6.2.4 enabling a generic clock generator a generic clock generator is enabled by writing a one to the generic clock generator enable bit in the generic clock generator control register (genctrl.genen). 15.6.2.5 disabling a generic clock generator a generic clock generator is disabled by writing a zero to genctrl.genen. when genctrl.genen is read as zero, the gclkgen clock is disabled and clock gated. 15.6.2.6 selecting a clock source for the generic clock generator each generic clock generator can individually select a clock source by writing to the source select bit group in genctrl (genctrl.src). changing from one clock source, a, to another clock source, b, can be done on the fly. if clock source b is not ready, the generic clock generator will c ontinue running with clock source a. as soon as clock source b is ready, however, the generic clock generator will switch to it. during the switching, the generic clock generator holds clock requests to clock sources a and b and then releases the clock source a request when the switch is done. the available clock sources are device dependent (usually the oscillators, rc oscillators, pll and dfll clocks). gclkgen[1] can be used as a common source for all t he generic clock generators except generic clock generator 1. 15.6.2.7 changing clock frequency the selected generic clock generator source, genclksrc can optionally be divided by writing a division factor gc lk_i o d ivide r c loc k g at e gc lk g en c lock s ource s 0 1 genctrl.divse l g en c trl. g enen g endiv.di v g enctrl.sr c gc lk g en s r c
87 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 in the division factor bit group in the generic clock gener ator division register (gendiv.div). depending on the value of the divide selection bit in genctrl (genctrl.divsel), it can be interpreted in two ways by the integer divider, as shown in table 15-1 . note that the number of div bits for each generic clock generator is device dependent. refer to table 15-10 for details. if genctrl.divsel is zero and gendiv.div is zero or one, the output clock will be undivided. 15.6.2.8 duty cycle 15.6.2.9 when dividing a clock with an odd division factor, the duty-cycle will not be 50/50. writing a one to the improve duty cycle bit in genctrl (genctrl.idc) will result in a 50/50 duty cycle. external clock each generic clock generator output clock (gclkgen) can be output. if the output enable bit in genctrl (genctrl.oe) is one and the generic clock generator is ena bled (genctrl.genen is one), the generic clock generator requests its clock source and the gclkgen clock is output to a gclk_io pin. if genctrl.oe is zero, gclk_io is set according to the output off value bit. if the output off value bit in genctrl (genctrl.oov) is zero, the output clock will be low when turned off. if genctrl .oov is one, the output clock will be high when turned off. in standby mode, if the clock is output (genctrl.oe is one) , the clock on the gclk_io pin is frozen to the oov value if the run in standby bit in genctrl (genctrl.runstdb y) is zero. if genctrl.runstdby is one, the gclkgen clock is kept running and output to gclk_io. 15.6.3 generic clock figure 15-4. generic clock 15.6.3.1 enabling a generic clock before a generic clock is enabled, one of the generic clock generators must be selected as the source for the generic clock by writing to clkctrl.gen. the clock source selection is individually set for each generic clock. when a generic clock generator has been selected, the generic cl ock is enabled by writing a one to the clock enable bit in clkctrl (clkctrl.clken). the clkctrl.clken bi t must be synchronized to the generic clock domain. clkctrl.clken will continue to read as its prev ious state until the synchronization is complete. table 15-1. division factor genctrl.divsel division factor 0 gendiv.div 1 2^(gendiv.div+1) c loc k g at e gclk_perip h c lkctrl.gen c lk c trl. c lken gclkgen [ 0 ] gc lk g en[1] gc lk g en[2] gclkgen [ n ]
88 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 15.6.3.2 disabling a generic clock a generic clock is disabled by writing a zero to clkctr l.clken. the clkctrl.clken bit must be synchronized to the generic clock domain and the clock actually switched off. clkctrl.clken will continue to read as its previous state until the synchronization is complete. when the generic clock is disabled, the generic clock is clock gated. 15.6.3.3 selecting a clock source for the generic clock when changing a generic clock source by writing to clkctrl. gen, the generic clock must be disabled before being re- enabled with the new clock source setting. this prevents glitches during the transition: a. write a zero to clkctrl.clken b. wait until clkctrl.clken reads as zero c. change the source of the generic clock by writing clkctrl.gen d. re-enable the generic clock by writing a one to clkctrl.clken 15.6.3.4 configuration lock the generic clock configuration is locked for further writ e accesses by writing the write lock bit (wrtlock) in the clkctrl register. all writes to the clkctrl register will be ignored. it can only be unlocked by a power reset. the generic clock generator sources of a ?locked? gener ic clock are also locked. the corresponding genctrl and gendiv are locked, and can be unlocked only by a power reset. there is one exception concerning the gclkgen[0]. as it is used as gclkmain, it can not be locked. it is reset by any reset to startup with a known configuration. the swrst can not unlock the registers. 15.6.4 additional features 15.6.4.1 indirect access the generic clock generator control and division regist ers (genctrl and gendiv) and the generic clock control register (clkctrl) are indirectly addressed as shown in figure 15-5 . figure 15-5. gclk indirect access writing these registers is done by setting the corresponding id bit group. to read a register, the user must write (byte access) the id of the channel, i, in the corresponding register. the value of the register for the corresponding id is avail able in the user interface by a read access. for example, the sequence to read the genctrl register of generic clock generator i is: a. do an 8-bit write of the i value to genctrl.id b. read genctrl genctr l g endiv c lk c tr l g en c trl.id= i g endiv.id= i clkctrl.id= j u ser interface genctr l g endiv gc lk g enerator [i ] c lk c tr l g clk[ j ]
89 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 15.6.4.2 generic clock enable after reset the generic clock controller must be able to provide a generic clock to some specific peripherals after a reset. that means that the configuration of the generic clock generators and generic clocks after reset is device-dependent. refer to table 15-8 and table 15-9 for details on genctrl reset. refer to table 15-12 and table 15-13 for details on gendiv reset. refer to table 15-4 and table 15-5 for details on clkctrl reset. 15.6.5 sleep mode operation 15.6.5.1 sleepwalking the gclk module supports the sleepwalking feature. du ring a sleep mode where the generic clocks are stopped, a peripheral that needs its generic clock to execute a process must request it from the generic clock controller. the generic clock controller will receive this request and then determine which generic clock generator is involved and which clock source needs to be awakened. it then wakes up the clock source, enables the generic clock generator and generic clock stages successively and delivers the generic clock to the peripheral. 15.6.5.2 run in standby mode in standby mode, the gclk can continuously output the generic clock generator output to gclk_io. refer to ?when dividing a clock with an odd division factor, the duty-cycle will not be 50/50. writing a one to the improve duty cycle bit in genctrl (genctrl.idc) will result in a 50/50 duty cycle.external clock? on page 87 for details. 15.6.6 synchronization due to the asynchronicity between clk_gclk_apb and gc lkgensrc some registers must be synchronized when accessed. a register can require: z synchronization when written z synchronization when read z synchronization when written and read z no synchronization when executing an operation that requires synchronization, the synchronization busy bit in the status register (status.syncbusy) will be set immediately, and cleared when synchronization is complete. if an operation that requires synchronization is executed wh ile status.syncbusy is one, the bus will be stalled. all operations will complete successfully, but the cpu will be stalled and interrupts will be pending as long as the bus is stalled. the following registers need synchronization when written: z generic clock generator control register (genctrl) z generic clock generator division register (gendiv) z control register (ctrl) write-synchronization is denoted by the write-sync hronization property in the register description. refer to the synchronization chapter for further details.
90 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 15.7 register summary offset name bit pos. 0x0 ctrl 7:0 swrst 0x1 status 7:0 syncbusy 0x2 clkctrl 7:0 id[5:0] 0x3 15:8 wrtlock clken gen[3:0] 0x4 genctrl 7:0 id[3:0] 0x5 15:8 src[4:0] 0x6 23:16 runstdby divsel oe oov idc genen 0x7 31:24 0x8 gendiv 7:0 id[3:0] 0x9 15:8 div[7:0] 0xa 23:16 div[15:8] 0xb 31:24
91 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 15.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the peri pheral access controller (pac). write-protection is denoted bythe write-protected property in each indivi dual register description. please refer to ?register access protection? on page 85 for details. some registers require synchronization when read and/or wr itten. synchronization is denoted by the write-synchronized or the read-synchronized property in each indi vidual register description. please refer to ?synchronization? on page 89 for details.
92 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 15.8.1 control name: ctrl offset: 0x0 reset: 0x00 property: write-protected, write-synchronized z bits 7:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? swrst: software reset 0: there is no reset operation ongoing. 1: there is a reset operation ongoing. writing a zero to this bit has no effect. writing a one to this bit resets all registers in the gclk to their initial state after a power reset, except for generic clocks and associated generators that have their wrtlock bit in clkctrl read as one. refer to table 15-8 for details on genctrl reset. refer to table 15-12 for details on gendiv reset. refer to table 15-4 for details on clkctrl reset. due to synchronization, there is a delay from writing ctrl.swrst until the reset is complete. ctrl.swrst and status.syncbusy will both be cleared when the reset is complete. bit76543210 swrst accessrrrrrrrr/w reset00000000
93 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 15.8.2 status name: status offset: 0x1 reset: 0x00 property: ? z bit 7 ? syncbusy: synchronization busy status this bit is cleared when the synchronization of registers between the clock domains is complete. this bit is set when the synchronization of registers between clock domains is started. z bits 6:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. bit76543210 syncbusy accessrrrrrrrr reset00000000
94 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 15.8.3 generic clock control this register allows the user to configure one of the generic cl ocks, as specified in the clkctrl.id bit group. to write to the clkctrl register, do a 16-bit write with all configurations and the id. to read the clkctrl register, first do an 8-bit write to t he clkctrl.id bit group with the id of the generic clock whose configuration is to be read, and then read the clkctrl register. name: clkctrl offset: 0x2 reset: 0x0000 property: write-protected z bit 15 ? wrtlock: write lock when this bit is written, it will lock from further writes the generic clock pointed to by clkctrl.id, the generic clock generator pointed to in clkctrl.gen and the division factor us ed in the generic clock generator. it can only be unlocked by a power reset. one exception to this is generic clock generator 0, which cannot be locked. 0: the generic clock and the associated generic clock generator and division factor are not locked. 1: the generic clock and the associated generic clock generator and division factor are locked. z bit 14 ? clken: clock enable this bit is used to enable and disable a generic clock. 0: the generic clock is disabled. 1: the generic clock is enabled. z bits 13:12 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 11:8 ? gen[3:0]: generic clock generator these bits select the generic clock generator to be used as the source of a generic clock. the value of the gen bit group versus generic clock generator is shown in table 15-2 . bit151413121110 9 8 wrtlock clken gen[3:0] access r/w r/w r r r/w r/w r/w r/w reset00000000 bit76543210 id[5:0] access r r r/w r/w r/w r/w r/w r/w reset00000000
95 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bits 7:6 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 5:0 ? id[5:0]: generic clock selection id these bits select the generic clock that will be configured. t he value of the id bit group versus module instance is shown in table 15-3 . table 15-2. generic clock generator value description 0x0 generic clock generator 0 0x1 generic clock generator 1 0x2 generic clock generator 2 0x3 generic clock generator 3 0x4 generic clock generator 4 0x5 generic clock generator 5 0x6 generic clock generator 6 0x7 generic clock generator 7 0x8-0xf reserved table 15-3. generic clock selection id value description 0x00 dfll48m reference 0x01 wdt 0x02 rtc 0x03 eic 0x04 evsys_channel_0 0x05 evsys_channel_1 0x06 evsys_channel_2 0x07 evsys_channel_3 0x08 evsys_channel_4 0x09 evsys_channel_5 0x0a evsys_channel_6 0x0b evsys_channel_7 0x0c sercomx_slow 0x0d sercom0_core 0x0e sercom1_core
96 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 a power reset will reset the clkctrl register for all ids, including the rtc. if the wrtlock bit of the corresponding id is zero and the id is not the rtc, a user reset will reset the clkctrl register for this id. after a power reset, the reset value of the clkctrl register versus module instance is as shown in table 15-4 . after a user reset, the reset value of the clkctrl register versus module instance is as shown in table 15-5 . 0x0f sercom2_core 0x10 sercom3_core 0x11 sercom4_core 0x12 sercom5_core 0x13 tc0,tc1 0x14 tc2,tc3 0x15 tc4,tc5 0x16 tc6,tc7 0x17 adc 0x18 ac_dig 0x19 ac_ana 0x1a dac 0x1b ptc 0x1c-0x3f reserved table 15-4. clkctrl reset value after a power reset module instance reset value after a power reset clkctrl.gen clkctrl.clken clkctrl.wrtlock rtc 0x00 0x00 0x00 wdt 0x02 0x01 if wdt enable bit in nvm user row written to one 0x00 if wdt enable bit in nvm user row written to zero 0x01 if wdt always-on bit in nvm user row written to one 0x00 if wdt always-on bit in nvm user row written to zero others 0x00 0x00 0x00 table 15-3. generic clock selection id (continued)
97 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 15-5. clkctrl reset value after a user reset module instance reset value after a user reset clkctrl.gen clkctrl.clken clkctrl.wrtlock rtc 0x00 if wrtlock=0 and clken=0 no change if wrtlock=1 or clken=1 0x00 if wrtlock=0 and clken=0 no change if wrtlock=1 or clken=1 no change wdt 0x02 if wrtlock=0 no change if wrtlock=1 if wrtlock=0 0x01 if wdt enable bit in nvm user row written to one 0x00 if wdt enable bit in nvm user row written to zero if wrtlock=1 no change no change others 0x00 if wrtlock=0 no change if wrtlock=1 0x00 if wrtlock=0 no change if wrtlock=1 no change
98 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 15.8.4 generic clock generator control this register allows the user to configure one of the generic clock generators, as specified in the genctrl.id bit group. to write to the genctrl register, do a 32-bi t write with all configurations and the id. to read the genctrl register, first do an 8-bit write to the genctrl.id bit group with the id of the generic clock generator twhose configuration is to be read, and then read the genctrl register. name: genctrl offset: 0x4 reset: 0x00010600 property: write-protected, write-synchronized z bits 31:22 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 21 ? runstdby: run in standby this bit is used to keep the generic clock generator running when it is configured to be output to its dedicated gclk_io pin. if genctrl.oe is zero, this bit has no e ffect and the generic clock generator will only be running if a peripheral requires the clock. 0: the generic clock generator is stopped in standby and the gclk_io pin state (one or zero) will be dependent on the setting in genctrl.oov. 1: the generic clock generator is kept running and out put to its dedicated gclk_io pin during standby mode. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 runstdby divsel oe oov idc genen access r r r/w r/w r/w r/w r/w r/w reset00000000 bit151413121110 9 8 src[4:0] access r r r r/w r/w r/w r/w r/w reset00000000 bit76543210 id[3:0] access r r r r r/w r/w r/w r/w reset00000000
99 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bit 20 ? divsel: divide selection this bit is used to decide how the clock source used by the generic clock generator will be divided. if the clock source should not be divided, the divsel bit must be zero and the gendiv.div value for the corresponding generic clock generator must be zero or one. 0: the generic clock generator equals the cl ock source divided by gendiv.div. 1: the generic clock generator equals the cloc k source divided by 2^(gendiv.div+1). z bit 19 ? oe: output enable this bit is used to enable output of the generated clock to gclk_io when gclk_io is not selected as a source in the genclk.src bit group. 0: the generic clock generator is not output. 1: the generic clock generator is output to the corresp onding gclk_io, unless the corresponding gclk_io is selected as a source in the genclk.src bit group. z bit 18 ? oov: output off value this bit is used to control the value of gclk_io when gclk_io is not selected as a source in the genclk.src bit group. 0: the gclk_io will be zero when the generic clock generator is turned off or when the oe bit is zero. 1: the gclk_io will be one when the generic clock gener ator is turned off or when the oe bit is zero. z bit 17 ? idc: improve duty cycle this bit is used to improve the duty cycle of the generic clock generator when odd division factors are used. 0: the generic clock generator duty cycle is not 50/50 for odd division factors. 1: the generic clock generator duty cycle is 50/50. z bit 16 ? genen: generic clock generator enable this bit is used to enable and disable the generic clock generator. 0: the generic clock generator is disabled. 1: the generic clock generator is enabled. z bits 15:13 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 12:8 ? src[4:0]: source select these bits define the clock source to be used as t he source for the generic clock generator, as shown in table 15- 6 .
100 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bits 7:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 3:0 ? id[3:0]: generic clock generator selection these bits select the generic clock generator that will be configured or read. the value of the id bit group versus which generic clock generator is configured is shown in table 15-7 . a power reset will reset the genctrl register for all ids, including the generic clock generator used by the rtc. if a generic clock generator id other than generic clock generator 0 is not a source of a ?locked? generic clock or a source of the rtc generic clock, a user reset will reset the genctrl for this id. after a power reset, the reset value of the genctrl register is as shown in table 15-8 . table 15-6. source select value name description 0x00 xosc xosc oscillator output 0x01 gclkio generator input pad 0x02 gclkgen[1] generic clock generator 1 output 0x03 osculp32k osculp32k oscillator output 0x04 osc32k osc32k oscillator output 0x05 xosc32k xosc32k oscillator output 0x06 osc8m osc8m oscillator output 0x07 dfll48m dfll48m output 0x08-0x1f reserved reserved for future use table 15-7. generic clock generator selection value description 0x0 generic clock generator 0 0x1 generic clock generator 1 0x2 generic clock generator 2 0x3 generic clock generator 3 0x4 generic clock generator 4 0x5 generic clock generator 5 0x6 generic clock generator 6 0x7 generic clock generator 7 0x8-0xf reserved
101 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 after a user reset, the reset value of the genctrl register is as shown in table 15-9 . . table 15-8. genctrl reset value after a power reset gclk generator id reset value after a power reset 0x00 0x00010600 0x01 0x00000001 0x02 0x00010302 0x03 0x00000003 0x04 0x00000004 0x05 0x00000005 0x06 0x00000006 0x07 0x00000007 table 15-9. genctrl reset value after a user reset gclk generator id reset value after a user reset 0x00 0x00010600 0x01 0x00000001 if the generator is not used by the rtc no change if the generator is used by the rt c or used by a gclk with a wrtlock as one 0x02 0x00010302 if the generator is not used by the rtc no change if the generator is used by the rt c or used by a gclk with a wrtlock as one 0x03 0x00000003 if the generator is not used by the rtc no change if the generator is used by the rt c or used by a gclk with a wrtlock as one 0x04 0x00000004 if the generator is not used by the rtc no change if the generator is used by the rt c or used by a gclk with a wrtlock as one 0x05 0x00000005 if the generator is not used by the rtc no change if the generator is used by the rt c or used by a gclk with a wrtlock as one 0x06 0x00000006 if the generator is not used by the rtc no change if the generator is used by the rt c or used by a gclk with a wrtlock as one 0x07 0x00000007 if the generator is not used by the rtc no change if the generator is used by the rt c or used by a gclk with a wrtlock as one
102 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 15.8.5 generic clock generator division this register allows the user to configure one of the gener ic clock generators, as specified in the gendiv.id bit group. to write to thegendiv register, do a 32-bit write with all configurations and the id. to read thegendiv register, first do an 8-bit write to the gendiv.id bit group with the id of the generic clock generator whose configuration is to be read, and then read the gendiv register. name: gendiv offset: 0x8 reset: 0x00000000 property: write-protected, write-synchronized z bits 31:24 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 23:8 ? div[15:0]: division factor these bits apply a division on each selected generic clo ck generator. the number of div bits each generator has can be seen in table 15-10 . writes to bits above the specified number will be ignored. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 div[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit151413121110 9 8 div[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 id[3:0] access r r r r r/w r/w r/w r/w reset00000000
103 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bits 7:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 3:0 ? id[3:0]: generic clock generator selection these bits select the generic clock generator on which the division factor will be applied, as shown in table 15-11 . a power reset will reset the gendiv register for all ids, including the generic clock generator used by the rtc. if a generic clock generator id other than generic clock generator 0 is not a source of a ?locked? genericclock or a source of the rtc generic clock, a user reset will reset the gendiv for this id. after a power reset, the reset value of the gendiv register is as shown in table 15-12 . table 15-10. division factor generator division factor bits generic clock generator 0 5 division factor bits - div[4:0] generic clock generator 1 16 division factor bits - div[15:0] generic clock generators 2 - 7 8 division factor bits - div[7:0] table 15-11. generic clock generator selection value description 0x0 generic clock generator 0 0x1 generic clock generator 1 0x2 generic clock generator 2 0x3 generic clock generator 3 0x4 generic clock generator 4 0x5 generic clock generator 5 0x6 generic clock generator 6 0x7 generic clock generator 7 0x8-0xf reserved
104 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 after a user reset, the reset value of the gendiv register is as shown in table 15-13 . table 15-12. gendiv reset value after a power reset gclk generator id reset value after a power reset 0x00 0x00000000 0x01 0x00000001 0x02 0x00000002 0x03 0x00000003 0x04 0x00000004 0x05 0x00000005 0x06 0x00000006 0x07 0x00000007 table 15-13. gendiv reset value after a user reset gclk generator id reset value after a user reset 0x00 0x00000000 0x01 0x00000001 if the generator is not used by the rtc no change if the generator is used by the rtc or used by a gclk with a wrtlock as one 0x02 0x00000002 if the generator is not used by the rtc no change if the generator is used by the rtc or used by a gclk with a wrtlock as one 0x03 0x00000003 if the generator is not used by the rtc no change if the generator is used by the rtc or used by a gclk with a wrtlock as one 0x04 0x00000004 if the generator is not used by the rtc no change if the generator is used by the rtc or used by a gclk with a wrtlock as one 0x05 0x00000005 if the generator is not used by the rtc no change if the generator is used by the rtc or used by a gclk with a wrtlock as one 0x06 0x00000006 if the generator is not used by the rtc no change if the generator is used by the rtc or used by a gclk with a wrtlock as one 0x07 0x00000007 if the generator is not used by the rtc no change if the generator is used by the rtc or used by a gclk with a wrtlock as one
105 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16. pm ? power manager 16.1 overview the power manager (pm) controls the reset, clock generation and power save modes of the microcontroller. utilizing a main clock chosen from a large number of clo ck sources from the gclk, the clock controller provides synchronous system clocks to the cpu and the modules c onnected to the ahb and the apbx bus. the synchronous system clocks are divided into a number of clock domains; one for the cpu and ahb and one for each apbx. any synchronous system clock can be changed at run-time during norma l operation. the clock domains can run at different speeds, enabling the user to save power by running peripherals at a relatively low clock frequency, while maintaining high cpu performance. in addition, the clock can be masked fo r individual modules, enabling the user to minimize power consumption. if for some reason the main clock stops oscillating, the clock failure detector allows switching the main clock to the safe osc8m clock. various sleep modes and clock gating are provided in order to fit power consumption requirements. this enables the microcontroller to stop unused modules to save power. in active mode, the cpu is executing application code. when the device enters a sleep mode, program execution is st opped and some modules and clock domains are automatically switched off by the pm according to the sleep mode. the application code decides which sleep mode to enter and when. interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from a sleep mode to active mode. the pm also contains a reset controller, which collects all possible reset sources. it issues a microcontroller reset and sets the device to its initial state, and allows the reset source to be identified by software. 16.2 features z reset control z reset the microcontroller and set it to an initial state according to the reset source z multiple reset sources z power reset sources: por, bod12, bod33 z user reset sources: external reset (reset ), watchdog timer reset, software reset z reset status register for reading the reset source from the application code z clock control z generates cpu, ahb and apb system clocks z multiple clock sources and division factor from gclk z clock prescaler with 1x to 128x division z safe run-time clock switching from gclk z module-level clock gating through maskable peripheral clocks z clock failure detector z power management control z sleep modes: idle, standby z sleepwalking support on apb and gclk clocks
106 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.3 block diagram figure 16-1. pm block diagram 16.4 signal description please refer to ?i/o multiplexing and considerations? on page 15 for details on the pin mapping for this peripheral. one signal can be mapped on several pins. 16.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 16.5.1 i/o lines not applicable. 16.5.2 power management not applicable. synchronous clock controller sleep mode controller reset controller cpu bod12 bod33 por wdt osc8m gclk reset sources peripherals reset clk_apb clk_ahb clk_cpu user reset power reset power manager cpu signal name type description reset digital input external reset
107 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.5.3 clocks the pm bus clock (clk_pm_apb) can be enabled and disabled in the power manager, and the default state of clk_pm_apb can be found in table 16-1 . if this clock is disabled in the power manager, it can only be re-enabled by a reset. a generic clock (gclk_main) is required to generate the main clock. this clock is configured by default in the generic clock controller, and can be re-configured by the user if needed. please refer to ?gclk ? generic clock controller? on page 83 for details. 16.5.3.1 main clock the main clock (clk_main) is the common source for the synchronous clocks. this is fed into the common 8-bit prescaler that is used to generate synchronous clocks to the cpu, ahb and apbx modules. 16.5.3.2 cpu clock the cpu clock (clk_cpu) is routed to the cpu. halting the cpu clock inhibits the cpu from executing instructions. 16.5.3.3 ahb clock the ahb clock (clk_ahb) is the root cl ock source used by peripherals requiring an ahb clock. the ahb clock is always synchronous to the cpu clock and has the same frequency, but may run even when the cpu clock is turned off. a clock gate is inserted from the common ahb cl ock to any ahb clock of a peripheral. 16.5.3.4 apbx clocks the apbx clock (clk_apbx) is the r oot clock source used by modules requi ring a clock on the apbx bus. the apbx clock is always synchronous to the cpu clock, but can be di vided by a prescaler, and will run even when the cpu clock is turned off. a clock gater is inserted from the common apb clock to any apbx clock of a module on apbx bus. 16.5.4 interrupts the interrupt request line is connected to the interrupt controller. using the pm interrupt requires the interrupt controller to be configured first. 16.5.5 events not applicable. 16.5.6 debug operation when the cpu is halted in debug mode, the pm continues normal operation. in sleep mode, the clocks generated from the pm are kept running to allow the debugger accessing any modules. as a consequence, power measurements are not possible in debug mode. 16.5.7 register access protection all registers with write access are optionally write-protec ted by the peripheral access controller (pac), except the following registers: z interrupt flag register (intflag) z reset cause register (rcause) write-protection is denoted by the write-protection property in the register description. write-protection does not apply for accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details. 16.5.8 analog connections not applicable.
108 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.6 functional description 16.6.1 principle of operation 16.6.1.1 synchronous clocks the gclk_main clock from gclk module pr ovides the source for the main clock, which is the common root for the synchronous clocks for the cpu and apbx modules. the main clock is divided by an 8-bit prescaler, and each of the derived clocks can run from any tapping off this prescaler or the undivided main clock, as long as f cpu f apbx . the synchronous clock source can be changed on the fly to respond to varying load in the application. the clocks for each module in each synchronous clock domain can be individually ma sked to avoid power consumption in inactive modules. depending on the sleep mode, some clock domains can be turned off. 16.6.1.2 reset controller the reset controller collects the various reset sources and generates resets for the device. the device contains a power-on-reset (por) detector, which keeps the system reset until power is stable. this eliminates the need for external reset circuitry to guarantee stable operation when powering up the device. 16.6.1.3 sleep mode controller in active mode, all clock domains are active, allowi ng software execution and peripheral operation. the pm sleep mode controller allows the user to choose between diff erent sleep modes depending on application requirements, to save power. 16.6.2 basic operation 16.6.2.1 initialization after a power-on reset, the pm is enabled and the reset c ause (rcause) register indicates the por source. the default clock source of the gclk_main clock is started and calibrated before the cpu st arts running. the gclk_main clock is selected as the main clock without any division on the prescaler. the device is in the active mode. by default, only the necessary clocks are enabled (see table 16-1 ). 16.6.2.2 enabling, disabling and resetting the pm module is always enabled and can not be reset. 16.6.2.3 selecting the main clock source refer to ?gclk ? generic clock controller? on page 83 for details on how to configure the main clock source. 16.6.2.4 selecting the synchronous clock division ratio the main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. by default, the synchronous clocks run on the undivided main clock. the user can select a prescaler division for the cpu clock by writing the cpu prescaler selection bits in the cpu sele ct register (cpusel.cpudiv), resulting in a cpu clock frequency determined by this equation: similarly, the clock for the apbx can be divided by writi ng their respective registers. to ensure correct operation, frequencies must be selected so that f cpu f apbx . also, frequencies must never exceed the specified maximum frequency for each clock domain. note that the ahb clock is always equal to the cpu clock. f cpu f main 2 cpudiv ---------------------- =
109 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 cpusel and apbxsel can be written without halting or dis abling peripheral modules. writing cpusel and apbxsel allows a new clock setting to be written to all synchronous clocks at the same time. it is possible to keep one or more clocks unchanged. this way, it is possible to, for example, scale the cpu speed according to the required performance, while keeping the apbx frequency constant. figure 16-2. synchronous clock selection and prescaler 16.6.2.5 clock ready flag there is a slight delay from when cpusel and apbxsel are written until the new clock setting becomes effective. during this interval, the clock ready flag in the interrupt flag status and clear register (intflag.ckrdy) will read as zero. if ckrdy in the intenset register is written to one, the power manager interrupt can be triggered when the new clock setting is effective. cksel must not be re-written while ckrdy is zero, or the system may become unstable or hang. 16.6.2.6 peripheral clock masking it is possible to disable or enable the clock for a peripheral in the ahb or apbx clock domain by writing the corresponding bit in the clock mask register (apbxm ask) to zero or one. refer to table 16-1 for the default state of each of the peripheral clocks. clock gate clock gate prescaler sleep controller sleep mode clk_ahb clock gate clock gate clk_apba clock gate clock gate clk_apbc clock gate clock gate clk_apbb apbcdiv apbbdiv apbadiv clk_ahb_ip0 clk_ahb_ip1 clk_ahb_ipn clk_apba_ip0 clk_apba_ip1 clk_apba_ipn clk_apbb_ip0 clk_apbb_ip1 clk_apbb_ipn clk_apbc_ip0 clk_apbc_ip1 clk_apbc_ipn apbcmask apbbmask apbamask cpudiv ahbmask clk_cpu gclk osc8m gclkmain bkupclk clock gate clock gate clock gate clock gate clock gate clock gate clock gate clock gate clock gate clock failure detector clk_main
110 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 when a module is not clocked, it will cease operation, and its registers cannot be read or written. the module can be re- enabled later by writing the corresponding mask bit to one. a module may be connected to several clock domains (for instance, ahb and apb), in which case it will have several mask bits. note that clocks should only be switched off if it is certain that the module will not be used. switching off the clock for the nvm controller (nvmctrl) will cause a problem if the cpu needs to read from the flash memory. switching off the clock to the power manager (pm), which contains the mask registers, or the corresponding apbx bridge, will make it impossible to write the mask registers again. in this case, they can only be re-enabled by a system reset. 16.6.2.7 clock failure detector this mechanism allows the main clock to be switched automatically to the safe osc8m clock when the main clock source is considered off. this may happen for instance when an ex ternal crystal oscillator is selected as the clock source for the main clock and the crystal fails. the mechanism is to designed to detect, during a osculp32k clock period, at least one rising edge of the main clock. if no rising edge is seen, the clock is considered failed. the clock failure detector is enabled by writing a one to the clock failure detector enable bit in ctrl (cfden.ctrl). as soon as the clock failure detector enable bit (ctrl.cfden) is one, the clock failure detector (cfd) will monitor the divided main clock. when a clock failure is detected, the main clock automatically switches to the osc8m clock and the clock failure detector flag in the interrupt flag status and clear register (intflag.cfd) is generated, if enabled. the bkupclk bit in the ctrl register is set by hardware to indicate that the main clock comes from osc8m. the table 16-1. peripheral clock default state peripheral clock default state clk_pac0_apb enabled clk_pm_apb enabled clk_sysctrl_apb enabled clk_gclk_apb enabled clk_wdt_apb enabled clk_rtc_apb enabled clk_eic_apb enabled clk_pac1_apb enabled clk_dsu_apb enabled clk_nvmctrl_apb enabled clk_port_apb enabled clk_pac2_apb disabled clk_sercomx_apb disabled clk_tcx_apb disabled clk_adc_apb enabled clk_ac_apb disabled clk_dac_apb disabled clk_ptc_apb disabled
111 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 gclkmain clock source can be selected again by writing a ze ro to the ctrl.bkupclk bit. writing the bit does not fix the failure, however. note 1: the detector does not monitor while the main clock is te mporarily unavailable (startup time after a wake-up, etc.) or in sleep mode. note 2: the clock failure detector must not be enabled if the source of the main clock is not significantly faster than the osculp32k clock. for instance, if gclkmain is the internal 32khz rc, then the clock failure detector must be disabled. 16.6.2.8 reset controller the latest reset cause is available in rcause, and can be read during the application boot sequence in order to determine proper action. there are two groups of reset sources: z power reset: resets caused by an electrical issue. z user reset: resets caused by the application. the table below lists the parts of the device that are reset, depending on the reset type. the external reset is generated when pulling the reset pin low. this pin has an internal pull-up, and does not need to be driven externally during normal operation. the por, bod12 and bod33 reset sources are generated by their corresponding module in the system controller interface (sysctrl). the wdt reset is generated by the watchdog timer. the system reset request (sysresetreq) is a software reset generated by the cpu when asserting the sysresetreq bit located in t he reset control register of the cpu (please see the arm ? cortex ? technical reference manual on http://www.arm.com ). table 16-2. effects of the different reset events power reset user reset por, bod12, bod33 external reset wdt reset, sysresetreq rtc all the 32khz sources wdt with alwayson feature gclk with wrtlock feature y n n debug logic y y n others y y y
112 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 16-3. reset controller 16.6.2.9 sleep mode controller sleep mode is activated by the wait for interrupt instru ction (wfi). the idle bits in the sleep mode register (sleep.idle) and the sleepdeep bit of the system control r egister of the cpu should be used as argument to select the level of the sleep mode. there are two main types of sleep mode: z idle mode: the cpu is stopped. optionally, some synchronous clock domains are stopped, depending on the idle argument. regulator operates in normal mode z standby mode: all clock sources are stopped, except thos e where the runstdby bit is set. regulator operates in low-power mode reset controller bod12 bod33 por wdt reset reset sources rtc 32khz clock sources wdt with alwayson gclk with wrtlock debug logic others cpu rcause table 16-3. sleep mode entry and exit table mode level mode entry wake-up sources idle 0 scr.sleepdeep = 0 sleep.idle=level wfi synchronous (apb, ahb), asynchronous 1 synchronous (apb), asynchronous 2 asynchronous standby scr.sleepdeep = 1 wfi asynchronous
113 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 notes: 1. refer to ?sysctrl ? system controller? on page 132 to determine the clock sources. 2. a clock source is demanded if either a module reques ts it or the clock source ondemand bit is set. idle mode the idle mode allows power optimization with the fastest wake-up time. the cpu is stopped. to further reduce power consumption, the user can disable the clocking of modules and clock sources by configuring the sleep.idle bit group. the module will be halted regardless of the bit settings of the mask registers in the power manager (pm.ahbmask, pm.apbxmask). regulator operates in normal mode. z entering idle mode: the idle mode is entered by exec uting the wfi instruction. additionally, if the sleeponexit bit in the arm cortex s ystem control register (scr) is se t, the idle mode will also be entered when the cpu exits the lowest priority isr. this mechanism can be useful for applications that only require the processor to run when an interrupt occurs. before entering the idle mode, the user must configure the idle mode configuration bit group and must write a zero to the scr.sleepdeep bit. z exiting idle mode: the processor wakes the system up when it detects any non-masked interrupt with sufficient priority to cause exception entry. the system goes back to the active mode. the cpu and affected modules are restarted. standby mode the standby modes allow achievi ng very low power consumption. in this mode, all clocks are stopped except those which are kept running if requested by a running module or have the ondemand bit set to zero. for example, the rtc can operate in standby mode. in this case, its gclk clock source will also be enabled. the regulator and the ram operate in low-power mode. a sleeponexit feature is also available. z entering standby mode: this mode is entered by executing the wfi instruction with the scr.sleepdeep bit of the cpu is written to 1. z exiting standby mode: any peripheral able to generate an asynchronous interrupt can wake up the system. for example, a module running on a gclk clock can tri gger an interrupt. when the enabled asynchronous wake-up event occurs and the system is woken up, the device will either execute the interrupt service routine or continue the normal program execution according to the priority mask register (primask) configuration of the cpu. 16.6.3 additional features 16.6.4 interrupts the peripheral has the following interrupt sources: sleep mode sleep. idle cpu clock ahb clock apb clock clock sources (1)(2) main clock regulator mode ram mode idle 0 stop run run run (if demanded) run normal normal 1 stop stop run run (if demanded) run 2 stop stop stop run (if demanded) run standby stop stop stop stop (if not demanded) stop low power low power
114 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z clock ready flag z clock failure detector each interrupt source has an interrupt flag associated with i t. the interrupt flag in the interrupt flag status and clear (intflag) register is set when the interrupt condition occu rs. each interrupt can be individually enabled by writing a one to the corresponding bit in the interrupt enable set (int enset) register, and disabled by writing a one to the corresponding bit in the interrupt enable clear (intenclr) r egister. an interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset. an interrupt flag is cleared by writing a one to the corresponding bit in the intflag register. each peripheral can have one interrupt request line per interrupt source or one common interrupt request line for all the interrupt sources. refer to ?nested vector interrupt controller? on page 28 for details. if the peripheral has one common interrupt request li ne for all the interrupt sources, the user must read the intflag register to determine which interrupt condition is present. 16.6.5 events not applicable. 16.6.6 sleep mode operation in all idle sleep modes, the power manager is still running on the selected main clock. in standdby sleep mode, the power manager is frozen and is able to go back to active mode upon any asynchronous interrupt.
115 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.7 register summary offset name bit pos. 0x00 ctrl 7:0 bkupclk cfden 0x01 sleep 7:0 idle[1:0] 0x02 reserved 0x03 reserved ? ? ? ? ? ? ? ? ? ? ? 0x06 reserved 0x07 reserved 0x08 cpusel 7:0 cpudiv[2:0] 0x09 apbasel 7:0 apbadiv[2:0] 0x0a apbbsel 7:0 apbbdiv[2:0] 0x0b apbcsel 7:0 apbcdiv[2:0] 0x0c reserved 0x0d reserved ? 0x12 reserved 0x13 reserved 0x14 ahbmask 7:0 nvmctrl dsu hpb2 hpb1 hpb0 0x15 15:8 0x16 23:16 0x17 31:24 0x18 apbamask 7:0 eic rtc wdt gclk sysctrl pm pac0 0x19 15:8 0x1a 23:16 0x1b 31:24 0x1c apbbmask 7:0 port nvmctrl dsu pac1 0x1d 15:8 0x1e 23:16 0x1f 31:24 0x20 apbcmask 7:0 sercom5 sercom4 sercom3 sercom2 sercom1 sercom0 evsys pac2 0x21 15:8 tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 0x22 23:16 ptc dac ac adc 0x23 31:24 0x24 reserved 0x25 reserved ? ? ? ? ? ? ? ? ? ? ? 0x32 reserved
116 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 0x33 reserved 0x34 intenclr 7:0 cfd ckrdy 0x35 intenset 7:0 cfd ckrdy 0x36 intflag 7:0 cfd ckrdy 0x37 reserved 0x38 rcause 7:0 syst wdt ext bod33 bod12 por offset name bit pos.
117 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit hal ves of a 16-bit register can be accessed directly. exception for apbasel, apbbsel and apbcsel: these registers must onl y be accessed with 8-bit access. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each individual register description. please refer to ?register access protection? on page 107 for details.
118 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8.1 control name: ctrl offset: 0x00 reset: 0x00 property: write-protected z bits 7:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 4 ? bkupclk: backup clock select this bit is set by hardware when a clock failure is detected. 0: the gclkmain clock is selected for the main clock. 1: the osc8m backup clock is selected for the main clock. z bit 3 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 2 ? cfden: clock failure detector enable 0: the clock failure detector is disabled. 1: the clock failure detector is enabled. z bits 1:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. bit 7 6 5 4 3 2 1 0 bkupclk cfden access r r r r/w r r/w r r reset 0 0 0 0 0 0 0 0
119 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8.2 sleep mode name: sleep offset: 0x01 reset: 0x00 property: write-protected z bits 7:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 1:0 ? idle[1:0]: idle mode configuration these bits select the idle mode configuration after a wfi instruction. bit76543210 idle[1:0] accessrrrrrrr/wr/w reset00000000 table 16-4. idle mode configuration idle[1:0] description 0x0 the cpu clock domain is stopped 0x1 the cpu and ahb clock domains are stopped 0x2 the cpu, ahb and apb clock domains are stopped 0x3 reserved
120 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8.3 cpu clock select name: cpusel offset: 0x08 reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 2:0 ? cpudiv[2:0]: cpu prescaler selection these bits define the division ratio of the main clock prescaler (2 n ). bit 76543210 cpudiv[2:0] accessrrrrrr/wr/wr/w reset00000000 table 16-5. cpu clock frequency ratio cpudiv[1:0] description 0x0 divide by 1 0x1 divide by 2 0x2 divide by 4 0x3 divide by 8 0x4 divide by 16 0x5 divide by 32 0x6 divide by 64 0x7 divide by 128
121 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8.4 apba clock select name: apbasel offset: 0x09 reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 2:0 ? apbadiv[2:0]: apba prescaler selection these bits define the division ratio of the apba clock prescaler (2 n ). bit76543210 apbadiv[2:0] access r r r r r r/w r/w r/w reset00000000 table 16-6. apba prescaler selection apbadiv[1:0] description 0x0 divide by 1 0x1 divide by 2 0x2 divide by 4 0x3 divide by 8 0x4 divide by 16 0x5 divide by 32 0x6 divide by 64 0x7 divide by 128
122 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8.5 apbb clock select name: apbbsel offset: 0x0a reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 2:0 ? apbbdiv[2:0]: apbb prescaler selection these bits define the division ratio of the apbb clock prescaler (2 n ). bit76543210 apbbdiv[2:0] accessrrrrrr/wr/wr/w reset00000000 table 16-7. apbb prescaler selection apbbdiv[1:0] description 0x0 divide by 1 0x1 divide by 2 0x2 divide by 4 0x3 divide by 8 0x4 divide by 16 0x5 divide by 32 0x6 divide by 64 0x7 divide by 128
123 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8.6 apbc clock select name: apbcsel offset: 0x0b reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 2:0 ? apbcdiv[2:0]: apbc prescaler selection these bits define the division ratio of the apbc clock prescaler (2 n ). bit76543210 apbcdiv[2:0] access r r r r r r/w r/w r/w reset00000000 table 16-8. apbc prescaler selection apbcdiv[1:0] description 0x0 divide by 1 0x1 divide by 2 0x2 divide by 4 0x3 divide by 8 0x4 divide by 16 0x5 divide by 32 0x6 divide by 64 0x7 divide by 128
124 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8.7 ahb mask name: ahbmask offset: 0x14 reset: 0x0000001f property: write-protected z bits 31:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 4:0 ? nvmctrl, dsu, hpb2 , hpb1, hpb0: ahb clock enable for any bit: 0: the ahb clock for the corresponding module is stopped. 1: the ahb clock for the corresponding module is enabled. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 accessrrrrrrrr reset00000000 bit151413121110 9 8 accessrrrrrrrr reset00000000 bit76543210 nvmctrl dsu hpb2 hpb1 hpb0 access r r r r/w r/w r/w r/w r/w reset00011111
125 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8.8 apba mask name: apbamask offset: 0x18 reset: 0x0000007f property: write-protected z bits 31:7 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 6:0 ? eic, rtc, wdt, gclk, sysctrl, pm, pac0: apb clock enable for any bit: 0: the apba clock for the corresponding module is stopped. 1: the apba clock for the corresponding module is enabled. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 accessrrrrrrrr reset00000000 bit151413121110 9 8 accessrrrrrrrr reset00000000 bit76543210 eic rtc wdt gclk sysctrl pm pac0 access r r/w r/w r/w r/w r/w r/w r/w reset01111111
126 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8.9 apbb mask name: apbbmask offset: 0x1c reset: 0x0000001f property: write-protected z bits 31:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 3:0 ? port, nvmctrl, dsu, pac1: apb clock enable for any bit: 0: the apbb clock for the corresponding module is stopped. 1: the apbb clock for the corresponding module is enabled. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 accessrrrrrrrr reset00000000 bit151413121110 9 8 accessrrrrrrrr reset00000000 bit76543210 port nvmctrl dsu pac1 access r r r r r/w r/w r/w r/w reset00011111
127 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8.10 apbc mask name: apbcmask offset: 0x20 reset: 0x00010000 property: write-protected z bits 31:20 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 19:0 ? ptc, dac, ac, adc, tc7, tc6, tc5, tc4, tc3, tc2, tc1, tc0, sercom5, sercom4, sercom3, sercom2, sercom1, sercom 0, evsys, pac2: apb clock enable for any bit: 0: the apbc clock for the corresponding module is stopped. 1: the apbc clock for the corresponding module is enabled. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 ptc dac ac adc access r r r r r/w r/w r/w r/w reset00000001 bit151413121110 9 8 tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 sercom5 sercom4 sercom3 sercom2 sercom1 sercom0 evsys pac2 access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
128 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8.11 interrupt enable clear this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interr upt enable set (intenset) register. name: intenclr offset: 0x34 reset: 0x00 property: write-protected z bits 7:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? cfd: clock failure detector interrupt enable 0: the clock failure detector interrupt is disabled. 1: the clock failure detector interrupt is enabled and an interrupt request will be generated when the clock fail- ure detector interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the clock failure detector interrupt enable bit and the corresponding interrupt request. z bit 0 ? ckrdy: clock ready interrupt enable 0: the clock ready interrupt is disabled. 1: the clock ready interrupt is enabled and will generate an interrupt request when the clock ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the clock ready in terrupt enable bit and the corresponding interrupt request. bit76543210 cfd ckrdy accessrrrrrrr/wr/w reset00000000
129 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8.12 interrupt enable set this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear (intenclr) register. name: intenset offset: 0x35 reset: 0x00 property: write-protected z bits 7:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? cfd: clock failure detector interrupt enable 0: the clock failure detector interrupt is disabled. 1: the clock failure detector interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the clock failure detector interrupt enable bit and enable the clock failure detec- tor interrupt. z bit 0 ? ckrdy: clock ready interrupt enable 0: the clock ready interrupt is disabled. 1: the clock ready interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the clock ready interrupt enable bit and enable the clock ready interrupt. bit76543210 cfd ckrdy accessrrrrrrr/wr/w reset00000000
130 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8.13 interrupt flag status and clear name: intflag offset: 0x36 reset: 0x00 property: ? z bits 7:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? cfd: clock failure detector this flag is cleared by writing a one to the flag. this flag is set on the next cycle after a clock failure detector occurs and will generate an interrupt request if intenclr/set.cfd is one. writing a zero to this bit has no effect. writing a one to this bit clears the clock failure detector interrupt flag. z bit 0 ? ckrdy: clock ready this flag is cleared by writing a one to the flag. this flag is set when the synchronous cpu and apbx clocks have frequencies as indicated in the cpusel and apbxsel registers, and will generate an interrupt if intenclr/set.ckrdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the clock ready interrupt flag. bit76543210 cfd ckrdy accessrrrrrrr/wr/w reset00000000
131 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 16.8.14 reset cause name: rcause offset: 0x38 reset: latest reset source property: ? z bit 7 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 6 ? syst: system reset request this bit is set if a system reset request has been performed. refer to the cortex processor documentation for more details. z bit 5 ? wdt: watchdog reset this flag is set if a watchdog timer reset occurs. z bit 4 ? ext: external reset this flag is set if an external reset occurs. z bit 3 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 2 ? bod33: brown out 33 detector reset this flag is set if a bod33 reset occurs. z bit 1 ? bod12: brown out 12 detector reset this flag is set if a bod12 reset occurs. z bit 0 ? por: power on reset this flag is set if a por occurs. bit76543210 syst wdt ext bod33 bod12 por accessrrrrrrrr reset0xxx0xxx
132 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 17. sysctrl ? system controller 17.1 overview the system controller (sysctrl) prov ides a user interface to the xosc , xosc32k, osc32k, osculp32k, osc8m, dfll48m, bod33, bod12, vreg and vref. through the interface registers, it is possible to enable, disable, calibrate and monitor the sysctrl sub-peripherals. all sub-peripheral statuses are collected in the power and cl ocks status register (pclksr). they can additionally trigger interrupts upon status changes via the inte nset, intenclr and intflag registers. additionally, bod33 and bod12 interrupts can be used to wake up the device from standby mode upon a programmed brown-out detection. 17.2 features z 0.4-32mhz crystal oscillator (xosc) z tunable gain control z programmable start-up time z crystal or external input clock on xin i/o z 32.768khz crystal oscillator (xosc32k) z automatic or manual gain control z programmable start-up time z crystal or external input clock on xin32 i/o z 32.768khz high accuracy internal oscillator (osc32k) z frequency fine tuning z programmable start-up time z 32.768khz ultra low power internal oscillator (osculp32k) z ultra low power, always-on oscillator z frequency fine tuning z calibration value loaded from flas h factory calibration at reset z 8mhz internal oscillator (osc8m) z fast startup z output frequency fine tuning z 4/2/1mhz divided output frequencies available z calibration value loaded from flas h factory calibration at reset z digital frequency locked loop (dfll48m) z internal oscillator with no external components z 48mhz output frequency z operates standalone as a high-frequency programmable oscillator in open loop mode z operates as an accurate frequency multiplier against a known frequency in closed loop mode z 3.3v brown-out detector (bod33) z programmable threshold z threshold value loaded from flas h user calibration at startup z triggers resets or interrupts z operating modes: z continuous mode z sampled mode for low power applications (programmable refresh frequency) z hysteresis z 1.2v brown-out detector (bod12) z programmable threshold z threshold value loaded from flas h user calibration at startup z triggers resets or interrupts z operating modes:
133 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z continuous mode z sampled mode for low power applications (programmable refresh frequency) z hysteresis z voltage reference system (vref) z bandgap voltage generator with programmable calibration value z temperature sensor z bandgap calibration value loaded from flash factory calibration at startup z voltage regulator system (vreg) z trimable core supply voltage level z voltage regulator trim value loaded from flash factory calibration at startup 17.3 block diagram figure 17-1. sysctrl block diagram xosc x osc 32 k osc3 2 k oscu lp 3 2k o sc8 m dfll48m bo d12 bo d 33 vo lta g e r eferen ce s y s te m vo lta ge r egulator s yste m osc illat o r s co ntr ol po wer m o nit or co ntr ol vo lta g e r eferen ce co ntr ol vo lta g e r egulator contro l s tat us ( pclksr re g ister ) interrupt s g enerat or i nterrupt s sysctrl
134 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 17.4 signal description the i/o lines are automatically selected when xosc or xosc32k are enabled. 17.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 17.5.1 i/o lines i/o lines are configured by sysctrl when either xosc or xosc32k are enabled, and need no user configuration. 17.5.2 power management the sysctrl can continue to operate in any sleep mode wher e the selected source clock is running. the sysctrl interrupts can be used to wake up the device from sleep m odes. the events can trigger other operations in the system without exiting sleep modes. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. 17.5.3 clocks the sysctrl gathers controls for all device oscillators and provides clock sources to the generic clock controller (gclk). the available clock sources are: xosc , xosc32k, osc32k, osculp32k, osc8m and dfll48m. the sysctrl bus clock (clk_sysctrl_apb) can be enabled and disabled in the power manager, and the default state of clk_sysctrl_apb can be found in the peripheral clock masking section in the ?pm ? power manager? on page 105 . the clock used by bod33 and bod12 in sampled mode is asynchronous to the user interface clock (clk_sysctrl_apb). likewise, the dfll48m control l ogic uses the dfll oscillator output, which is also asynchronous to the user interface clock (clk_sysctrl_apb). due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. refer to ?synchronization? on page 143 for further details. 17.5.4 interrupts the interrupt request line is connected to the interrupt cont roller. using the sysctrl interrupts requires the interrupt controller to be configured first. refer to ?nested vector interrupt controller? on page 28 for details. 17.5.5 debug operation when the cpu is halted in debug mode, the sysctrl continues normal operation. if the sysctrl is configured in a way that requires it to be periodically serviced by the cpu through interrupts or similar, improper operation or data loss may result during debugging. if a debugger connection is detected by the system, bod33 and bod12 resets will be blocked. signal name type description xin analog input multipurpose crystal oscillator or external clock generator input xout analog output external multipurpose crystal oscillator output xin32 analog input 32khz crystal oscillator or external clock generator input xout32 analog output 32khz crystal oscillator output
135 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 17.5.6 register access protection all registers with write-access are optionally write-protect ed by the peripheral access controller (pac), except the following registers: z interrupt flag status and clear register (intflag) write-protection is denoted by the write-protection property in the register description. when the cpu is halted in debug mode, all wr ite-protection is automatically disabled. write-protection does not apply for accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details. 17.5.7 analog connections the 32.768khz crystal must be connected between the xin32 and xout32 pins, and the 0.4-32mhz crystal must be connected between the xin and xout pins, along with any required load capacitors. 17.6 functional description 17.6.1 principle of operation xosc, xosc32k, osc32k, osculp32k, osc8m, dfll48m, bod33, bod12, vreg and vref are configured via sysctrl control registers. through this interface, the sub-peripherals are enabled, disabled or have their calibration values updated. the power and clocks status register gathers different status signals coming from the sub-peripherals controlled by the sysctrl. the status signals can be used to generate system in terrupts, and in some cases wake up the system from standby mode, provided the corresponding interrupt is enabled. 17.6.2 external multipurpose crystal oscillator (xosc) operation the xosc can operate in two different modes: c. external clock, with an external clock signal connected to the xin pin d. crystal oscillator, with an external 0.4-32mhz crystal the xosc can be used as a clock source for generic clock generators, as described in the ?gclk ? generic clock controller? on page 83 chapter. at reset, the xosc is disabled, and the xin/xout pins can be used as general purpose i/o (gpio) pins or by other peripherals in the system. when xosc is enabled, the operating mode determines the gpio usage. when in crystal oscillator mode, the xin and xout pins are controlled by the sysctrl, and gpio functions are overridden on both pins. when in external clock mode, the only xin pin will be overridden and controlled by the sysctrl, while the xout pin can still be used as a gpio pin. the xosc is enabled by writing a one to the enable bit in the external multipurpose crystal oscillator control register (xosc.enable). to enable the xosc as a crystal oscillator , the xtal enable bit (xosc.xtalen) must written to one. if xosc.xtalen is zero, external clock input will be enabled. when in crystal oscillator mode (xosc.xtalen is one), the external multipurpose crystal oscillator gain (xosc.gain) must be set to match the external crystal oscillator frequency. if the external multipurpose crystal oscillator automatic amplitude gain control (xosc.ampgc) is one, the oscillato r amplitude will be automatically adjusted, and in most cases result in a lower power consumption. the xosc will behave differently in different sleep modes based on the settings of xosc.runstdby, xosc.ondemand and xosc.enable:
136 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 after a hard reset, or when waking up from a sleep mode where the xosc was disabled, the xosc will need a certain amount of time to stabilize on the correct frequency. this start-up time can be configured by changing the oscillator start-up time bit group (xosc. startup) in the external multipurpose crystal oscillator control register. during the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. the external multipurpose crystal oscillator ready bit in the power and clock status register (pclks r.xoscrdy) is set when the external clock or crystal oscillator is stable and ready to be used as a clock source. an interrupt is generated on a zero- to-one transition on pclksr.xoscrdy if the external multipur pose crystal oscillator ready bit in the interrupt enable set register (intenset.xoscrdy) is set. 17.6.3 32khz external crystal oscillator (xosc32k) operation the xosc32k can operate in two different modes: 1. external clock, with an external clock signal connected to xin32 2. crystal oscillator, with an external 32.768khz crystal connected between xin32 and xout32 the xosc32k can be used as a source for generic clock generators, as described in the ?gclk ? generic clock controller? on page 83 chapter. at power-on, reset the xosc32k is disabled, and the xin 32/xout32 pins can be used as general purpose i/o (gpio) pins or by other peripherals in the system. when xosc32k is enabled, the operating mode determines the gpio usage. when in crystal oscillator mode, xin32 and xout32 are cont rolled by the sysctrl, and gpio functions are overridden on both pins. when in external clock mode, only the xin32 pin will be overridden and controlled by the sysctrl, while the xout32 pin can still be used as a gpio pin. the external clock or crystal oscillator is enabled by writ ing a one to the enable bit (xosc32k.enable) in the 32khz external crystal oscillator control register. to enable the xo sc32k as a crystal oscillator, a one must be written to the xtal enable bit (xosc32k.xtalen) . if xosc32k.xtalen is zero, external clock input will be enabled. the oscillator is disabled by writing a zero to the enable bit (xosc32k.enable) in the 32khz external crystal oscillator control register while keeping the other bits unchanged. writi ng to the xosc32k.enable bit while writing to other bits may result in unpredictable behavior. the oscillator remains enabled in all sleep modes if it has been enabled beforehand. the start-up time of the 32khz external crystal osci llator is selected by writing to the oscillator start-up time bit group (xosc32k.startup) in the in the 32khz ex ternal crystal oscillator control register. the sysctrl masks the oscillator output during the start-up time to ensure that no unstable clock propagates to the digital logic. the 32khz external crystal oscillator ready bit (pclksr.xosc32krdy) in the power and clock status register is set when the oscillator is stable and ready to be used as a clo ck source. an interrupt is gener ated on a zero-to-one transition xosc.runstdby xosc.ondemand xosc.enable sleep behavior - - 0 disabled 0 0 1 always run in idle sleep modes. disabled in standby sleep mode. 0 1 1 only run in idle sleep modes if requested by a peripheral. disabled in standby sleep mode. 1 0 1 always run in idle and standby sleep modes. 1 1 1 only run in idle or standby sleep modes if requested by a peripheral.
137 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 of pclksr.xosc32krdy if the 32khz external crystal oscillator ready bit (intenset.xosc32krdy) in the interrupt enable set register is set. as a crystal oscillator usually requires a very long start-up time (up to one second), the 32khz external crystal oscillator will keep running across resets, except for power-on reset (por). the xosc32k has a 32.768khz output enabled by writing a one to the 32khz external crystal oscillator 32khz output enable bit (xosc32k.en32k) in the 32khz external crystal oscillator control register. the xosc32k also has a 1.024khz clock output enabled by writing a one to the 32khz external crystal oscillator 1khz output enable bit (xosc32k.en1k) in the external 32khz crystal oscilla tor control register. xosc32k.en32k and xosc32k.en1k are only usable when xin32 is connected to a crystal, and not when an external digital clock is applied on xin32. 17.6.4 32khz internal osc illator (osc32k) operation the osc32k provides a tunable, low-speed and low-power clock source. the osc32k can be used as a source for the generic clock generators, as described in the ?gclk ? generic clock controller? on page 83 chapter. the osc32k is disabled by default. the osc32k is enabled by writing a one to the 32khz internal oscillator enable bit (osc32k.enable) in the 32khz internal oscillator control regi ster. it is disabled by writing a zero to osc32k.enable. the osc32k has a 32.768khz output enabled by writing a one to the 32khz internal oscillator 32khz output enable bit (osc32k.en32k). the osc32k also has a 1.024khz clock output enabled by writing a one to the 32khz internal oscillator 1khz output enable bit (osc32k.en1k). the frequency of the osc32k oscillator is controlled by the value in the 32khz internal oscillator calibration bits (osc32k.calib) in the 32khz internal oscillator control r egister. the calib value must be written by the user. flash factory calibration values are stored in the non-volatile memory . when writing to the calibration bits, the user must wait for the pclksr.osc32krdy bit to go high before the value is committed to the oscillator. 17.6.5 32khz ultra low power internal oscillator (osculp32k) operation the osculp32k provides a tunable, low-speed and ultra- low-power clock source. the osculp32k is factory- calibrated under typical voltage and temperature conditions. the osculp32k should be preferred to the osc32k whenever the power requirements are prevalent over frequency stability and accuracy. the osculp32k can be used as a source for the generic clock generators, as described in the ?gclk ? generic clock controller? on page 83 chapter. the osculp32k is enabled by default after a power-on reset (por) and will always run except during por. the osculp32k has a 32.768khz output and a 1.024khz output that are always running. the frequency of the osculp32k oscillator is controlled by the value in the 32khz ultra low power internal oscillator calibration bits (osculp32k.calib) in the 32khz ultr a low power internal oscillator control register. osculp32k.calib is automatically loaded from flash factory calibration during startup, and is used to compensate for process variation. the calibration value can be over ridden by the user by writing to osculp32k.calib. 17.6.6 8mhz internal oscillator (osc8m) operation osc8m is an internal oscillator operating in open-loop m ode and generating an 8mhz frequency. the osc8m is factory- calibrated under typical voltage and temperature conditions. osc8m is the default clock source that is used after a pow er-on reset (por). the osc8m can be used as a source for the generic clock generators, as described in the ?gclk ? generic clock controller? on page 83 chapter, as well as function as the backup clock if a main clock failure is detected. osc8m is enabled by writing a one to the oscillator enab le bit (osc8m.enable) in the osc8m control register, and disabled by writing a zero to this bit. when enabling osc8 m, osc8m.enable must be read back until it reads one. the user must ensure that the osc8m is fully disabled before enabling it, and that the osc8m is fully enabled before disabling it by reading osc8m.enable.
138 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 the frequency of the osc8m oscillator is controlled by the va lue in the calibration bits (osc8m.calib) in the osc8m control register. calib is automatically loaded from flash factory calibration dur ing startup, and is used to compensate for process variation. the user can control the oscillation frequency by writing to the frequency range (frange) and calibration (calib) bit groups in the 8mhz rc oscillator control register (o sc8m). the frange and calib bit groups should only be updated when the osc8m is disabled. as this is in open-loop mode, the frequency will be voltage, temperature and process dependent. osc8m is automatically switched off in certain sleep m odes to reduce power consumption, as described in the ?pm ? power manager? on page 105 chapter. 17.6.7 digital frequency locked loop (dfll48m) operation the dfll48m can operate in both open-loop mode and closed-l oop mode. in closed-loop mode, a low-frequency clock with high accuracy can be used as the reference clock to get high accuracy on the output clock (clk_dfll48m). the dfll48m can be used as a source for the generic clock generators, as described in the ?gclk ? generic clock controller? on page 83 chapter. 17.6.7.1 basic operation open-loop operation after any reset, the open-loop mode is selected. when operating in open-loop mode, the output frequency of the dfll48m will be determined by the values written to the dfll coarse value bit group and the dfll fine value bit group (dfllval.coarse and dfllval.fi ne) in the dfll value register. it is possible to change the values of dfllval.coarse and dfllval.fine and thereby the output frequency of the dfll48m output clock, clk_dfll48m, while the dfll48m is enabled and in use. clk_dfll48m is ready to be used when pclksr.dfllrdy is set after enabling the dfll48m. closed-loop operation in closed-loop operation, the output frequency is continu ously regulated against a reference clock. once the multiplication factor is set, the oscillator fine tuning is aut omatically adjusted. the dfll48m must be correctly configured before closed-loop operation can be enabled. after enabling t he dfll48m, it must be configured in the following way: 1. enable and select a reference clock (clk_dfll48m_r ef). clk_dfll48m_ref is generic clock channel 0 (dfll48m_reference). refer to ?gclk ? generic clock controller? on page 83 chapter for details. 2. select the maximum step size allowed in finding the coarse and fine values by writing the appropriate values to the dfll coarse maximum step and dfll fine ma ximum step bit groups (dfllmul.cstep and dfll- mul.fstep) in the dfll multiplier register. a small st ep size will ensure low overshoot on the output frequency, but will typically result in longer lock times. a high val ue might give a large overshoot, but will typically provide faster locking. dfllmul.cstep and dfllmul.fstep shoul d not be higher than 50% of the maximum value of dfllval.coarse and dfllval.fine, respectively. 3. select the multiplication factor in the dfll multiply fa ctor bit group (dfllmul.mul) in the dfll multiplier regis- ter. care must be taken when choosing dfllmul.mul so that the output frequency does not exceed the maximum frequency of the device. if the target frequency is below the minimum frequency of the dfll48m, the output frequency will be equal to the dfll minimum frequency. 4. start the closed loop mode by writing a one to the df ll mode selection bit (dfllctrl.mode) in the dfll con- trol register. the frequency of clk_dfll48m (f clkdfll48m ) is given by: f clkdfll 48 m dfllmul mul f clkdfll 48 mref ? =
139 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 where f clkdfll48mref is the frequency of the reference clo ck (clk_dfll48m_ref). dfllval.coarse and dfllval.fine are read-only in closed-loop mode, and are controlled by the frequency tuner shown in figure 17-1 to meet user specified frequency. in closed-loop mode, the va lue in dfllval.coarse is used by the frequency tuner as a starting point for coarse. writing dfllval.coarse to a value close to the final value before entering closed-oop mode will reduce the time needed to get a lock on coarse. frequency locking the locking of the frequency in closed-loop mode is divided into two stages. in the first, coarse stage, the control logic quickly finds the correct value for dfllval.coarse and sets the output frequency to a value close to the correct frequency. on coarse lock, the dfll locked on coarse value bit (pclksr.dflllockc) in the power and clocks status register will be set. in the second, fine stage, the control logic tunes the value in dfllval.fine so that the output frequency is very close to the desired frequency. on fine lock, the dfll locked on fine value bit (pclksr.dflllockf) in the power and clocks status register will be set. interrupts are generated by both pclksr.dflllockc and pclksr.dflllockf if intenset.dfllockc or intenset.dfllockf are written to one. clk_dfll48m is ready to be used when the dfll ready bi t (pclksr.dfllrdy) in the power and clocks status register is set, but the accuracy of the output frequency depends on which locks are set. frequency error measurement the ratio between clk_dfll48m_ref and clk48m_dfll is m easured automatically when the dfll48m is in closed- loop mode. the difference between this ratio and the value in dfllmul.mul is stored in the dfll multiplication ratio difference bit group(dfllval.diff) in the dfll value regist er . the relative error on clk_dfll48m compared to the target frequency is calculated as follows: drift compensation if the stable dfll frequency bit (dfllctrl.stable) in the df ll control register is zero, the frequency tuner will automatically compensate for drift in the clk_dfll48m without losing either of the locks. this means that dfllval.fine can change after every measurement of cl k_dfll48m. if the dfllval.fine value overflows or underflows due to large drift in temperature and/or volt age, the dfll out of bounds bit (pclksr.dflloob) in the power and clocks status register will be set. after an out of bounds error condition, the user must rewrite dfllmul.mul to ensure correct clk_ dfll48m frequency. an interrupt is generated on a zero-to-one transition on pclksr.dflloob if the dfll out of b ounds bit (intenset.dflloob) in the inte rrupt enable set register is set. this interrupt will also be set if the tuner is not able to lock on the correct coarse value. reference clock stop detection if clk_dfll48m_ref stops or is running at a ve ry low frequency (slower than clk_dfll48m/(2 * mul max )), the dfll reference clock stopped bit (pclksr.dfllrcs) in the po wer and clocks status register will be set. detecting a stopped reference clock can take a long time, on the order of 2 17 clk_dfll48m cycles. when the reference clock is stopped, the dfll48m will operate as if in open-loop mode. closed-loop mode operation will automatically resume if the clk_dfll48m_ref is restarted. an interrupt is generat ed on a zero-to-one transition on pclksr.dfllrcs if the dfll reference clock stopped bit (intenset.dfllrcs) in the interrupt enable set register is set. 17.6.7.2 additional features dealing with delay in the dfll in closed-loop mode the time from selecting a new clk_dfll48m frequency until this frequency is output by the dfll48m can be up to several microseconds. if the value in dfllmul.mul is small, this can lead to instability in the dfll48m locking mechanism, which can prevent the dfll48m from achieving locks. to avoid this, a chill cycle, during which the clk_dfll48m frequency is not measured, can be enabled. the chill cycle is enabled by default, but can be disabled by error diff mul -------------- =
140 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 writing a one to the dfll chill cycle disable bit (dfllctrl.ccd is) in the dfll control register. enabling chill cycles might double the lock time. another solution to this problem consists of using less strict lock requirements. this is called quick lock (ql), which is also enabled by default, but it can be disabled by writing a o ne to the quick lock disable bit (dfllctrl.qldis) in the dfll control register. the quick lock might lead to a larger spread in the output frequency than chill cycles, but the average output frequency is the same. wake from sleep modes dfll48m can optionally reset its lock bits when it is disabled. this is configured by the lose lock after wake bit (dfllctrl.llaw) in the dfll control register. if dfllc trl.llaw is zero, the dfll48m will be re-enabled and start running with the same configuration as before being disabled, even if the reference clock is not available. the locks will not be lost. when the reference clock has restarted, the fine tracking will quickly compensate for any frequency drift during sleep if dfllctrl.stable is zero. if dfllctrl.ll aw is one when disabling the dfll48m, the dfll48m will lose all its locks, and needs to regain these through the full lock sequence. accuracy there are three main factors that determine the accuracy of f clkdfll48m . these can be tuned to obtain maximum accuracy when fine lock is achieved. z fine resolution: the frequency step between two fine values. this is relatively smaller for high output frequencies. z resolution of the measurement: if the resolution of the measured f clkdfll48m is low, i.e., the ratio between the clk_dfll48m frequency and the clk_dfll48m_ref frequency is small, then the dfll48m might lock at a frequency that is lower than the targeted frequency. it is recommended to use a reference clock frequency of 32khz or lower to avoid this issue for low target frequencies. z the accuracy of the reference clock. 17.6.8 brown-out de tector operation the sysctrl provides user control to two brown-out detectors (bod) monitoring two supply domains. one bod monitors the 3.3v vddana supply (bod33), and a sec ond bod monitors the 1.2v vddcore supply (bod12). both brown-out detectors support continuous or sampling modes. for each bod, the threshold value action (reset the device or generate an interrupt) as well as the enable/disable settings are loaded from flash user calibration at start up, and can be overridden by writing to the corresponding user register bit groups. 17.6.8.1 3.3v brown-out detector (bod33) the 3.3v brown-out detector (bod33) monitors the vdda na supply and compares the voltage with the brown-out threshold level set in the bod33 level bit group (bod33.leve l) in the bod33 register. the brown-out detector can generate either an interrupt or a reset when vddana cro sses below the brown-out threshold level. the bod33 detection status can be read from the bod33 detection bit (pclksr.bod33det) in the power and clocks status register. at startup or at power-on reset (por), the bod33 regist er values are loaded from the flash user row. refer to ?non- volatile memory (nvm) user row mapping? on page 25 for more details. 17.6.8.2 1.2v brown-out detector (bod12) the 1.2v brown-out detector (bod12) monitors the vd dcore supply and compares the voltage with the brown-out threshold level set in the bod12 level bit group (bod12.leve l) in the bod12 register. the bod12 can generate either an interrupt or a reset when vddcore crosses below the br own-out threshold level. the bod12 detection status can be read from the bod12 detection bit (pclksr.bod12det) in the power and clocks status register. at startup or at power-on reset (por), the bod12 regist er values are loaded from the flash user row. refer to ?non- volatile memory (nvm) user row mapping? on page 25 for more details.
141 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 17.6.8.3 continuous mode when the bod33 mode bit (bod33.mode) in the bod33 register is written to zero and the bod33 is enabled (bod33.enable is written to one), the bod33 operates in c ontinuous mode. in this mode, the bod33 is continuously monitoring the vddana supply voltage. when the bod12 mode bit (bod12.mode) in the bod12 register is written to zero and the bod12 is enabled (bod12.enable is written to one), the bod12 operates in c ontinuous mode. in this mode, the bod12 is continuously monitoring the vddcore supply voltage. continuous mode is the default mode for both bod12 and bod33. 17.6.8.4 sampling mode the sampling mode is a low-power mode where the bod33 or bod12 is being repeatedly enabled on a sampling clock?s ticks. the bod33 or bod12 will monitor the supply voltage for a short period of time and then go to a low-power disabled state until the next sampling clock tick. sampling mode is enabled by writing one to bod33.mode for bod33, and by writing one to bod12.mode for bod12. the frequency of the clock ticks (f clksampling ) is controlled by the bod33 prescaler select bit group (bod33.psel) in the bod33 register and prescaler select bit group(bod12.psel ) in the bod12 bod12 register for bod33 and bod12, respectively. the prescaler signal (f clkprescaler ) is a 1khz clock, output from the32khz ultra low power oscillator, osculp32k. as the sampling mode clock is different from the apb clock domain, synchronization among the clocks is necessary. figure 17-2 shows a block diagram of the sampling mode. the bod33 and bod12 synchronization ready bits (pclksr.b33srdy and pclksr.b12srdy, respectively) in the power and clocks status register show the synchronization ready status of the synchronizer. writing attempts to the bod33 register are ignored while pclksr.b33srdy is zero. writing attempts to the bod 12 register are ignored while pclksr.b12srdy is zero. figure 17-2. sampling mode block diagram the bod33 clock enable bit (bod33.cen) in the bod33 regi ster and the bod12 clock enable bit (bod12.cen) in the bod12 register should always be disabled before changing the prescaler value. to change the prescaler value for the bod33 or bod12 during sampling mode, the following steps need to be taken: 1. wait until the pclksr.b33srdy bi t or the pclksr.b12srdy bit is set. 2. write the selected value to the bod33.psel or bod12.psel bit group. f clksampling f clkprescaler 2 psel 1 + () ------------------------------ = us er interfa ce r e g i s ter s ( apb clock domain ) p re sc ale r ( clk_prescale r domain ) s yn c hr o nizer p s el c en mo de enabl e c lk_apb c lk_pre sc aler c lk _ samplin g
142 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 17.6.8.5 hysteresis the hysteresis functionality can be used in both continuous and sampling mode. writing a one to the bod33 hysteresis bit (bod33.hyst) in the bod33 register will add hysteresis to the bod33 threshold level. writing a one to the bod12 hysteresis bit (bod12.hyst) in the bod12 register will add hysteresis to the bod12 threshold level. 17.6.9 voltage regulator system operation the embedded voltage regulator (vreg) is an internal voltage regulator that provides the core logic supply (vddcore). 17.6.9.1 user control of the voltage regulator system the voltage regulator is enabled after any reset, and can be disabled by writing a zero to the enable bit (vreg.enable) of the vreg register. the voltage regulator output supply level is determined by the level bit group (vreg.level) value in the vreg register. at reset, the vreg.level register value is loaded from flash factory calibration. via the vddcore monitoring bit group (vreg.v ddmon), it is possible to monitor the core supply voltage so that if it drops below a critical level, a power-on reset is applied. t he device is allowed to restart executing code only after the core supply voltage is restored to an acceptable level. the threshold at which this system triggers is significantly lower than the 1.2v brown-out detector's own threshold (bod12). this can, therefore, be seen as a complementary voltage monitoring feature. 17.6.10 voltage reference system operation the voltage reference system (vref) consists of a b andgap reference voltage generator and a temperature sensor. the bandgap reference voltage generator is factory-calibrated under typical voltage and temperature conditions. at reset, the vref.cal register value is loaded from flash factory calibration. the temperature sensor can be used to get an absolute te mperature in the temperature range of cmin to cmax degrees celsius. the sensor will output a linear voltage propor tional to the temperature. to calculate the temperature from a measured voltage, the following formula can be used: 17.6.10.1 user control of th e voltage regulator system ito enable the temperature sensor, write a one the temperatur e sensor enable bit (vref.tsen) in the vref register. the temperature sensor can be redirected to the adc fo r conversion. the bandgap reference voltage generator output can also be routed to the adc if the bandgap output enabl e bit (vref.bgouten) in t he vref register is set. the bandgap reference voltage generator output level is deter mined by the calib bit group (vref.calib) value in the vref register.the default calibration value can be ove rridden by the user by writing to the calib bit group. 17.6.11 interrupts the sysctrl has the following interrupt sources: z xoscrdy - multipurpose crystal oscillator ready: a 0 to 1 transition on the pclksr.xoscrdy bit is detected z xosc32krdy - 32khz crystal oscillator ready: a 0 to 1 transition on the pclksr.xosc32krdy bit is detected z osc32krdy - 32khz internal oscillator ready: a 0 to 1 transition on the pclksr.osc32krdy bit is detected z osc8mrdy - 8mhz internal oscillator ready: a 0 to 1 transition on the pclksr.osc8mrdy bit is detected z dfllrdy - dfll48m ready: a 0 to 1 transiti on on the pclksr.dfllrdy bit is detected z dflloob - dfll48m out of boundaries: a 0 to 1 trans ition on the pclksr.dflloob bit is detected z dflllockf - dfll48m fine lock: a 0 to 1 transition on the pclksr.dflllockf bit is detected c min vmes vout max ? () temperature voltage ------------------------------------ +
143 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z dflllockc - dfll48m coarse lock: a 0 to 1 transition on the pclksr.dflllockc bit is detected z dfllrcs - dfll48m reference clock has stopped: a 0 to 1 transition on the pclksr.dfllrcs bit is detected z bod33rdy - bod33 ready: a 0 to 1 transiti on on the pclksr.bod33rdy bit is detected z bod33det - bod33 detection: a 0 to 1 trans ition on the pclksr.bod33det bit is detected z b33srdy - bod33 synchronization ready: a 1 to 0 transition on the pclksr.b33srdy bit is detected z bod12rdy - bod12 ready: a 0 to 1 transiti on on the pclksr.bod12rdy bit is detected z bod12det - bod12 detection: a 0 to 1 trans ition on the pclksr.bod12det bit is detected z b12srdy - bod12 synchronization ready: a 1 to 0 transition on the pclksr.b12srdy bit is detected each interrupt source has an interrupt flag associated with i t. the interrupt flag in the interrupt flag status and clear register (intflag) is set when the interrupt condition occu rs. each interrupt can be individually enabled by writing a one to the corresponding bit in the interrupt enable set regi ster (intenset), and disabled by writing a one to the corresponding bit in the interrupt enable clear register (int enclr). an interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the sysctrl is reset. s ee the intflag register for details on how to clear interrupt flags. the sysctrl has one common interrupt request line for all t he interrupt sources.the user must read the intflag register to determine which interrupt condition is present. refer to the chapter for details. note that interrupts must be globally enabled for interrupt requests to be generated. refer to the ?nested vector interrupt controller? on page 28 chapter for details. 17.6.12 synchronization due to the multiple clock domains, values in the dfll48m control registers need to be synchronized to other clock domains. the status of this synchronization can be read fr om the power and clocks status register (pclksr). before writing to any of the dfll48m control registers, the user must check that the dfll ready bit (pclksr.dfllrdy) in pclksr is set to one. when this bit is set, the dfll48m can be configured and clk_dfll48m is ready to be used. any write to any of the dfll48m control registers while dfllrdy is zero will be ignored. an interrupt is generated on a zero- to-one transition of dfllrdy if the dfllrdy bit (intense t.dflldy) in the interrupt enable set register is set. in order to read from any of the dfll48m configuration registers, the user must request a read synchronization by writing a one to dfllsync.readreq. the registers can be read only when pclksr.dfllrdy is set. if dfllsync.readreq is not written before a read, a synchronization will be started, and the bus will be halted until the synchronization is complete. reading the dfll48m registers when the dfll48m is dsiabled will not halt the bus. rsimplythe prescaler counter used to trigger one-shot brow n-out detections also operates asynchronously from the peripheral bus. as a consequence, the prescaler register s require synchronization when written or read. the synchronization results in a delay from when the initializat ion of the write or read operation begins until the operation is complete. the write-synchronization is triggered by a write to the bod 12 or bod33 control register. the synchronization ready bit (pclksr.b12srdy or pclksr .b33srdy) in the pclksr register wi ll be cleared when the write-synchronization starts and set when the write-synchronization is complete. when the write-synchronization is ongoing (pclksr.b33srdy or pclksr.b12srdy is zero), an attempt to do any of the following will cause the peripheral bus to stall until the synchronization is complete: z writing to the bod33 or bod12 control register z reading the bod33 or bod12 control register that was written the user can either poll pclksr.b12srdy or pc lksr.b33srdy or use t he intenset.b12srdy or intenset.b33srdy interrupts to check when the synchronizati on is complete. it is also possible to perform the next read/write operation and wait, as this next operation will be completed after the ongoing read/write operation is synchronized.
144 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.7 register summary table 17-1. sysctrl register summary (sheet 1 of 2) offset name bit pos. 0x00 intenclr 7:0 dflllckc dflllckf dflloob dfllrdy osc8mrdy osc32krdy xosc32krdy xoscrdy 0x01 15:8 b12srdy bod12det bod12rdy b33srdy bod33det bod33rdy dfllrcs 0x02 23:16 0x03 31:24 0x04 intenset 7:0 dflllckc dflllckf dflloob dfllrdy osc8mrdy osc32krdy xosc32krdy xoscrdy 0x05 15:8 b12srdy bod12det bod12rdy b33srdy bod33det bod33rdy dfllrcs 0x06 23:16 0x07 31:24 0x08 intflag 7:0 dflllckc dflllckf dflloob dfllrdy osc8mrdy osc32krdy xosc32krdy xoscrdy 0x09 15:8 b12srdy bod12det bod12rdy b33srdy bod33det bod33rdy dfllrcs 0x0a 23:16 0x0b 31:24 0x0c pclksr 7:0 dflllckc dflllckf dflloob dfllrdy osc8mrdy osc32krdy xosc32krdy xoscrdy 0x0d 15:8 b12srdy bod12det bod12rdy b33srdy bod33det bod33rdy dfllrcs 0x0e 23:16 0x0f 31:24 0x10 xosc 7:0 ondemand runstdby xtalen enable 0x11 15:8 startup[3:0] ampgc gain[2:0] 0x12 reserved 0x13 reserved 0x14 xosc32k 7:0 ondemand runstdby aampen en1k en32k xtalen enable 0x15 15:8 wrtlock startup[2:0] 0x16 reserved 0x17 reserved 0x18 osc32k 7:0 ondemand runstdby en1k en32k enable 0x19 15:8 wrtlock startup[2:0] 0x1a 23:16 calib[6:0] 0x1b 31:24 0x1c osculp32k 7:0 wrtlock calib[4:0] 0x1d reserved 0x1e reserved 0x1f reserved 0x20 osc8m 7:0 ondemand runstdby enable 0x21 15:8 presc[1:0] 0x22 23:16 calib[7:0] 0x23 31:24 frange[1:0] calib[11:8] 0x24 dfllctrl 7:0 ondemand runstdby llaw stable mode enable 0x25 15:8 qldis ccdis 0x26 reserved 0x27 reserved
145 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 0x28 dfllval 7:0 fine[7:0] 0x29 15:8 coarse[4:0] 0x2a 23:16 diff[7:0] 0x2b 31:24 diff[15:8] 0x2c dfllmul 7:0 mul[7:0] 0x2d 15:8 mul[15:8] 0x2e 23:16 fstep[7:0] 0x2f 31:24 cstep[4:0] 0x30 dfllsync 7:0 readreq 0x31 reserved 0x32 reserved 0x33 reserved 0x34 bod33 7:0 runstdby action[1:0] hyst enable 0x35 15:8 psel[3:0] cen mode 0x36 23:16 level[5:0] 0x37 31:24 0x38 bod12 7:0 runstdby action[1:0] hyst enable 0x39 15:8 psel[3:0] cen mode 0x3a 23:16 level[4:0] 0x3b 31:24 0x3c vreg 7:0 runstdby vddmon[1:0] enable 0x3d 15:8 calib[2:0] level[2:0] 0x3e reserved 0x3f reserved 0x40 vref 7:0 bgouten tsen 0x41 15:8 0x42 23:16 calib[7:0] 0x43 31:24 calib[10:8] table 17-1. sysctrl register summary (sheet 2 of 2) offset name bit pos.
146 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each individual register des cription. please refer to the register access protection section and the pac chapter for details. some registers require synchronization when read and/or written. synchronization is denoted by the synchronized property in each individual register description. refer to ?synchronization? on page 143 for details.
147 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.1 interrupt enable clear this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable set register (intenset). name: intenclr offset: 0x00 reset: 0x00000000 property: write-protected z bits 31:15 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 14 ? b12srdy: bod12 synchron ization ready in terrupt enable 0: the bod12 synchronization ready interrupt is disabled. 1: the bod12 synchronization ready interrupt is enabl ed, and an interrupt request will be generated when the bod12 synchronization ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the bod12 synchroniza tion ready interrupt enable bit, disable the bod12 syn- chronization ready interrupt and clear the corresponding interrupt request. z bit 13 ? bod12det: bod12 de tection interrupt enable 0: the bod12 detection interrupt is disabled. 1: the bod12 detection interrupt is enabled, and an interrupt request will be generated when the bod12 detec- tion interrupt flag is set. bit3130292827 26 25 24 access r r r r r r r r reset 0 0 0 0 0 0 0 0 bit2322212019 18 17 16 access r r r r r r r r reset 0 0 0 0 0 0 0 0 bit15141312 11 10 9 8 b12srdy bod12det bod12rdy b33srdy bod33det bod33rdy dfllrcs access r r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 dflllckc dflllckf dflloob dfllrdy osc8mrdy osc32krdy xosc32krdy xoscrdy access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0
148 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 writing a zero to this bit has no effect. writing a one to this bit will clear the bod12 detection interrupt enable bit, disable the bod12 detection interrupt and clear the corresponding interrupt request. z bit 12 ? bod12rdy: bod12 ready interrupt enable 0: the bod12 ready interrupt is disabled. 1: the bod12 ready interrupt is enabled and an interrupt request will be generated when the bod12 ready inter- rupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the bod12 ready interrupt enable bit, disable the bod12 ready interrupt and clear the corresponding interrupt request. z bit 11 ? b33srdy: bod33 synchr onization ready interrupt enable 0: the bod33 synchronization ready interrupt is disabled. 1: the bod33 synchronization ready interrupt is enabl ed, and an interrupt request will be generated when the bod33 synchronization ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the bod33 synchroniza tion ready interrupt enable bit, disable the bod33 syn- chronization ready interrupt and clear the corresponding interrupt request. z bit 10 ? bod33det: bod33 de tection interrupt enable 0: the bod33 detection interrupt is disabled. 1: the bod33 detection interrupt is enabled, and an interrupt request will be generated when the bod33 detec- tion interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the bod33 detection interrupt enable bit, disable the bod33 detection interrupt and clear the corresponding interrupt request. z bit 9 ? bod33rdy: bod33 ready interrupt enable 0: the bod33 ready interrupt is disabled. 1: the bod33 ready interrupt is enabled, and an interrupt request will be generated when the bod33 ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the bod33 ready interrupt enable bit, disable the bod33 ready interrupt and clear the corresponding interrupt request. z bit 8 ? dfllrcs: dfll reference clock stopped interrupt enable 0: the dfll reference clock stopped interrupt is disabled. 1: the dfll reference clock stopped interrupt is enabled, and an interrupt request will be generated when the dfll reference clock stopped interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the dfll reference clock stopped interrupt enable bit, disable the dfll refer- ence clock stopped interrupt and clear the corresponding interrupt request. z bit 7 ? dflllckc: dfll lo ck coarse interrupt enable 0: the dfll lock coarse interrupt is disabled. 1: the dfll lock coarse interrupt is enabled, and an interrupt request will be generated when the dfll lock coarse interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the dfll lock coarse interrupt enable bit, disable the dfll lock coarse inter- rupt and clear the corresponding interrupt request.
149 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 z bit 6 ? dflllckf: dfll lock fine interrupt enable 0: the dfll lock fine interrupt is disabled. 1: the dfll lock fine interrupt is enabled, and an interrupt request will be generated when the dfll lock fine interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the dfll lock fine interrupt enable bit, disable the dfll lock fine interrupt and clear the corresponding interrupt request. z bit 5 ? dflloob: dfll out of bounds interrupt enable 0: the dfll out of bounds interrupt is disabled. 1: the dfll out of bounds interrupt is enabled, and an interrupt request will be generated when the dfll out of bounds interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the dfll out of bounds interrupt enable bit, disable the dfll out of bounds interrupt and clear the corresponding interrupt request. z bit 4 ? dfllrdy: dfll ready interrupt enable 0: the dfll ready interrupt is disabled. 1: the dfll ready interrupt is enabled, and an interrupt request will be generated when the dfll ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the dfll ready interr upt enable bit, disable the dfll ready interrupt and clear the corresponding interrupt request. z bit 3 ? osc8mrdy: osc8m ready interrupt enable 0: the osc8m ready interrupt is disabled. 1: the osc8m ready interrupt is enabled, and an interrupt request will be generated when the osc8m ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the osc8m ready interrupt enable bit, disable the osc8m ready interrupt and clear the corresponding interrupt request. z bit 2 ? osc32krdy: osc32k ready interrupt enable 0: the osc32k ready interrupt is disabled. 1: the osc32k ready interrupt is enabled, and an interrupt request will be generated when the osc32k ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the osc32k ready interrupt enable bit, disable the osc32k ready interrupt and clear the corresponding interrupt request. z bit 1 ? xosc32krdy: xosc32k ready interrupt enable 0: the xosc32k ready interrupt is disabled. 1: the xosc32k ready interrupt is enabled, and an interrupt request will be generated when the xosc32k ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the xosc32k ready interrupt enable bit, disable the xosc32k ready interrupt and clear the corresponding interrupt request. z bit 0 ? xoscrdy: xosc ready interrupt enable 0: the xosc ready interrupt is disabled. 1: the xosc ready interrupt is enabled, and an interrupt request will be generated when the xosc ready inter- rupt flag is set.
150 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 writing a zero to this bit has no effect. writing a one to this bit will clear the xosc ready interrupt enable bit, disable the xosc ready interrupt and clear the corresponding interrupt request.
151 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.2 interrupt enable set this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear register (intenclr). name: intenset offset: 0x04 reset: 0x00000000 property: write-protected z bits 31:15 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 14 ? b12srdy: bod12 synchron ization ready in terrupt enable 0: the bod12 synchronization ready interrupt is disabled. 1: the bod12 synchronization ready interrupt is enabl ed, and an interrupt request will be generated when the bod12 synchronization ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will set the bod12 synchroniza tion ready interrupt disable/enable bit, disable the bod12 synchronization ready interrupt and set the corresponding interrupt request. z bit 13 ? bod12det: bod12 de tection interrupt enable 0: the bod12 detection interrupt is disabled. 1: the bod12 detection interrupt is enabled, and an interrupt request will be generated when the bod12 detec- tion interrupt flag is set. bit31302928 27 26 25 24 access r r r r r r r r reset0000 0 0 0 0 bit23222120 19 18 17 16 access r r r r r r r r reset0000 0 0 0 0 bit15141312 11 10 9 8 b12srdy bod12det bod12rdy b33srdy bod33det bod33rdy dfllrcs access r r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 dflllckc dflllckf dflloob dfllrdy osc8mrdy osc32krdy xosc32krdy xoscrdy access r/w r/w r/w r/w r/w r/w r/w r/w reset0000 0 0 0 0
152 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 writing a zero to this bit has no effect. z bit 12 ? bod12rdy: bod12 ready interrupt enable 0: the bod12 ready interrupt is disabled. 1: the bod12 ready interrupt is enabled, and an interrupt request will be generated when the bod12 ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will set the bod12 ready interrupt disable/enable bit, disable the bod12 ready interrupt and set the corresponding interrupt request. z bit 11 ? b33srdy: bod33 synchr onization ready interrupt enable 0: the bod33 synchronization ready interrupt is disabled. 1: the bod33 synchronization ready interrupt is enabl ed, and an interrupt request will be generated when the bod33 synchronization ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will set the bod33 synchroniza tion ready interrupt disable/enable bit, disable the bod33 synchronization ready interrupt and set the corresponding interrupt request. z bit 10 ? bod33det: bod33 de tection interrupt enable 0: the bod33 detection interrupt is disabled. 1: the bod33 detection interrupt is enabled, and an interrupt request will be generated when the bod33 detec- tion interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will set the bod33 detection interrupt disable/enable bit, disable the bod33 detection interrupt and set the corresponding interrupt request. z bit 9 ? bod33rdy: bod33 ready interrupt enable 0: the bod33 ready interrupt is disabled. 1: the bod33 ready interrupt is enabled, and an interrupt request will be generated when the bod33 ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will set the bod33 ready interrupt disable/enable bit, disable the bod33 ready interrupt and set the corresponding interrupt request. z bit 8 ? dfllrcs: dfll reference clock stopped interrupt enable 0: the dfll reference clock stopped interrupt is disabled. 1: the dfll reference clock stopped interrupt is enabled, and an interrupt request will be generated when the dfll reference clock stopped interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will set the dfll reference clock stopped interrupt disable/enable bit, disable the dfll reference clock stopped interrupt and set the corresponding interrupt request. z bit 7 ? dflllckc: dfll lo ck coarse interrupt enable 0: the dfll lock coarse interrupt is disabled. 1: the dfll lock coarse interrupt is enabled, and an interrupt request will be generated when the dfll lock coarse interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will set the dfll lock coarse interrupt disable/enable bit, disable the dfll lock coarse interrupt and set the corresponding interrupt request. z bit 6 ? dflllckf: dfll lock fine interrupt enable 0: the dfll lock fine interrupt is disabled.
153 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 1: the dfll lock fine interrupt is enabled, and an interrupt request will be generated when the dfll lock fine interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will set the dfll lock fine interrupt disable/enable bit, disable the dfll lock fine inter- rupt and set the corresponding interrupt request. z bit 5 ? dflloob: dfll out of bounds interrupt enable 0: the dfll out of bounds interrupt is disabled. 1: the dfll out of bounds interrupt is enabled, and an interrupt request will be generated when the dfll out of bounds interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will set the dfll out of bounds interrupt disable/enable bit, disable the dfll out of bounds interrupt and set the corresponding interrupt request. z bit 4 ? dfllrdy: dfll ready interrupt enable 0: the dfll ready interrupt is disabled. 1: the dfll ready interrupt is enabled, and an interrupt request will be generated when the dfll ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will set the dfll ready interrupt disable/enable bit, disable the dfll ready interrupt and set the corresponding interrupt request. z bit 3 ? osc8mrdy: osc8m ready interrupt enable 0: the osc8m ready interrupt is disabled. 1: the osc8m ready interrupt is enabled, and an interrupt request will be generated when the osc8m ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will set the osc8m ready interrupt disable/enable bit, disable the osc8m ready inter- rupt and set the corresponding interrupt request. z bit 2 ? osc32krdy: osc32k ready interrupt enable 0: the osc32k ready interrupt is disabled. 1: the osc32k ready interrupt is enabled, and an interrupt request will be generated when the osc32k ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will set the osc32k ready interrupt disable/enable bit, disable the osc32k ready inter- rupt and set the corresponding interrupt request. z bit 1 ? xosc32krdy: xosc32k ready interrupt enable 0: the xosc32k ready interrupt is disabled. 1: the xosc32k ready interrupt is enabled, and an interrupt request will be generated when the xosc32k ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will set the xosc32k ready interrupt disable/enable bit, disable the xosc32k ready interrupt and set the corresponding interrupt request. z bit 0 ? xoscrdy: xosc ready interrupt enable 0: the xosc ready interrupt is disabled. 1: the xosc ready interrupt is enabled, and an interrupt request will be generated when the xosc ready inter- rupt flag is set. writing a zero to this bit has no effect.
154 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.3 interrupt flag status and clear name: intflag offset: 0x08 reset: 0x00000000 property: - z bits 31:15 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 14 ? b12srdy: bod12 synchronization ready this flag is cleared by writing a one to it. this flag is set on a zero-to-one transition of the bod 12 synchronization ready bit in the status register (pclksr.b12srdy) and will generate an interr upt request if intenset.b12srdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the bod12 synchronization ready interrupt flag. z bit 13 ? bod12det: bod12 detection this flag is cleared by writing a one to it. this flag is set on a zero-to-one transition of the bod12 detection bit in the status register (pclksr.bod12det) and will generate an interrupt request if intenset.bod12det is one. writing a zero to this bit has no effect. writing a one to this bit clears the bod12 detection interrupt flag. bit313029282726 25 24 access r r r r r r r r reset000000 0 0 bit232221201918 17 16 access r r r r r r r r reset000000 0 0 bit151413121110 9 8 b12srdy bod12det bod12rdy b33srdy bod33det bod33rdy dfllrcs access r r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 dflllckc dflllckf dflloob dfllrdy osc8mrdy osc32krdy xosc32krdy xoscrdy access r/w r/w r/w r/w r/w r/w r/w r/w reset000000 0 0
155 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 z bit 12 ? bod12rdy: bod12 ready this flag is cleared by writing a one to it. this flag is set on a zero-to-one transition of the bod12 ready bit in the status register (pclksr.bod12rdy) and will generate an interrupt request if intenset.bod12rdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the bod12 ready interrupt flag. z bit 11 ? b33srdy: bod33 synchronization ready this flag is cleared by writing a one to it. this flag is set on a zero-to-one transition of the bod 33 synchronization ready bit in the status register (pclksr.b33srdy) and will generate an interr upt request if intenset.b33srdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the bod33 synchronization ready interrupt flag z bit 10 ? bod33det: bod33 detection this flag is cleared by writing a one to it. this flag is set on a zero-to-one transition of the bod33 detection bit in the status register (pclksr.bod33det) and will generate an interrupt request if intenset.bod33det is one. writing a zero to this bit has no effect. writing a one to this bit clears the bod33 detection interrupt flag. z bit 9 ? bod33rdy: bod33 ready this flag is cleared by writing a one to it. this flag is set on a zero-to-one transition of the bod33 ready bit in the status register (pclksr.bod33rdy) and will generate an interrupt request if intenset.bod33rdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the bod33 ready interrupt flag. z bit 8 ? dfllrcs: dfll reference clock stopped this flag is cleared by writing a one to it. this flag is set on a zero-to-one transition of the dfll reference clock stopped bit in the status register (pclksr.dfllrcs) and will generate an interrupt request if intenset.dfllrcs is one. writing a zero to this bit has no effect. writing a one to this bit clears the dfll reference clock stopped interrupt flag. z bit 7 ? dflllckc: dfll lock coarse this flag is cleared by writing a one to it. this flag is set on a zero-to-one transition of the dfll lock coarse bit in the status register (pclksr.dflll- ckc) and will generate an interrupt request if intenset.dflllckc is one. writing a zero to this bit has no effect. writing a one to this bit clears the dfll lock coarse interrupt flag. z bit 6 ? dflllckf: dfll lock fine this flag is cleared by writing a one to it. this flag is set on a zero-to-one transition of the dfll lock fine bit in the status register (pclksr.dflllckf) and will generate an interrupt request if intenset.dflllckf is one. writing a zero to this bit has no effect. writing a one to this bit clears the dfll lock fine interrupt flag. z bit 5 ? dflloob: dfll out of bounds this flag is cleared by writing a one to it.
156 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 this flag is set on a zero-to-one transition of the dfll ou t of bounds bit in the status register (pclksr.dfl- loob) and will generate an interrupt request if intenset.dflloob is one. writing a zero to this bit has no effect. writing a one to this bit clears the dfll out of bounds interrupt flag. z bit 4 ? dfllrdy: dfll ready this flag is cleared by writing a one to it. this flag is set on a zero-to-one transition of the dfll ready bit in the status register (pclksr.dfllrdy) and will generate an interrupt reques t if intenset.dfllrdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the dfll ready interrupt flag. z bit 3 ? osc8mrdy: osc8m ready this flag is cleared by writing a one to it. this flag is set on a zero-to-one transition of the osc8m ready bit in the status register (pclksr.osc8mrdy) and will generate an interrupt request if intenset.osc8mrdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the osc8m ready interrupt flag. z bit 2 ? osc32krdy: osc32k ready this flag is cleared by writing a one to it. this flag is set on a zero-to-one transition of the osc32k ready bit in the status register (pclksr.osc32krdy) and will generate an interrupt request if intenset.osc32krdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the osc32k ready interrupt flag. z bit 1 ? xosc32krdy: xosc32k ready this flag is cleared by writing a one to it. this flag is set on a zero-to-one transition of the xosc32k ready bit in the status register (pclksr.xosc32krdy) and will generate an inte rrupt request if intenset.xosc32krdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the xosc32k ready interrupt flag. z bit 0 ? xoscrdy: xosc ready this flag is cleared by writing a one to it. this flag is set on a zero-to-one transition of the xosc ready bit in the status register (pclksr.xoscrdy) and will generate an interrupt reques t if intenset.xoscrdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the xosc ready interrupt flag.
157 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.4 power and clocks status name: pclksr offset: 0x0c reset: 0x00000000 property: - z bits 31:15 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 14 ? b12srdy: bod12 synchronization ready 0: bod12 synchronization is ongoing. 1: bod12 synchronization is complete. z bit 13 ? bod12det: bod12 detection 0: no bod12 detection. 1: bod12 has detected that the core power supply is going below the bod12 reference value. z bit 12 ? bod12rdy: bod12 ready 0: bod12 is not ready. 1: bod12 is ready. z bit 11 ? b33srdy: bod33 synchronization ready 0: bod33 synchronization is ongoing. 1: bod33 synchronization is complete. bit313029282726 25 24 access r r r r r r r r reset 0 0 0 0 0 0 0 0 bit232221201918 17 16 access r r r r r r r r reset 0 0 0 0 0 0 0 0 bit1514131211 10 9 8 b12srdy bod12det bod12rdy b33srdy bod33det bod33rdy dfllrcs access r r r r r r r r reset 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 dflllckc dflllckf dflloob dfllrdy osc8mrdy osc32krdy xosc32krdy xoscrdy access r r r r r r r r reset 0 0 0 0 0 0 0 0
158 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 z bit 10 ? bod33det: bod33 detection 0: no bod33 detection. 1: bod33 has detected that the i/o power supply is going below the bod33 reference value. z bit 9 ? bod33rdy: bod33 ready 0: bod33 is not ready. 1: bod33 is ready. z bit 8 ? dfllrcs: dfll reference clock stopped 0: dfll reference clock is running. 1: dfll reference clock has stopped. z bit 7 ? dflllckc: dfll lock coarse 0: no dfll coarse lock detected. 1: dfll coarse lock detected. z bit 6 ? dflllckf: dfll lock fine 0: no dfll fine lock detected. 1: dfll fine lock detected. z bit 5 ? dflloob: dfll out of bounds 0: no dfll out of bounds detected. 1: dfll out of bounds detected. z bit 4 ? dfllrdy: dfll ready 0: dfll is not ready. 1: dfll is stable and ready to be used as a clock source. z bit 3 ? osc8mrdy: osc8m ready 0: osc8m is not ready. 1: osc8m is stable and ready to be used as a clock source. z bit 2 ? osc32krdy: osc32k ready 0: osc32k is not ready. 1: osc32k is stable and ready to be used as a clock source. z bit 1 ? xosc32krdy: xosc32k ready 0: xosc32k is not ready. 1: xosc32k is stable and ready to be used as a clock source. z bit 0 ? xoscrdy: xosc ready 0: xosc is not ready. 1: xosc is stable and ready to be used as a clock source.
159 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.5 external multipurpose crystal oscillator (xosc) control name: xosc offset: 0x10 reset: 0x0080 property: write-protected z bits 15:12 ? startup[3:0]: start-up time these bits select start-up time for the oscillator according to table 17-2 . the osculp32k oscillator is used to clock the start-up counter. bit151413121110 9 8 startup[3:0] ampgc gain[2:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 ondemand runstdby xtalen enable access r/w r/w r r r r/w r/w r reset10000000 table 17-2. start-uptime for external multipurpose crystal oscillator startup[3:0] number of osculp32k clock cycles approximate equivalent time 0x0 1 32s 0x1 2 64s 0x2 4 128s 0x3 8 256 0x4 16 512s 0x5 32 1ms 0x6 64 2ms 0x7 128 4ms 0x8 256 8ms 0x9 512 16ms 0xa 1024 32ms 0xb 2048 64ms 0xc 4096 128ms 0xd 8192 256ms 0xe 16384 512ms 0xf 32768 1s
160 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 z bit 11 ? ampgc: automatic amplitude gain control 0: the automatic amplitude gain control is disabled. 1: the automatic amplitude gain control is enabled. amplitude gain will be automatically adjusted during crystal oscillator operation. z bits 10:8 ? gain[2:0]: oscillator gain these bits select the gain for the oscillator, given in table table 17-3 . the listed maximum frequencies are recom- mendations, and might vary based on capacitive load and crystal characteristics. setting this bit group has no effect when the automatic amplitude gain control is active. z bit 7 ? ondemand: on demand control the on demand operation mode allows an oscillator to be enabled or disabled, depending on peripheral clock requests. in on demand operation mode, i.e., if the xosc.ondemand bit has been previously written to one, the oscillator will be running only when requested by a peripheral. if t here is no peripheral requesting the oscillator?s clock source, the oscillator will be in a disabled state. if on demand is disabled, the oscillator will always be running when enabled. in standby sleep mode, the on demand operation is still active if the xosc.runstdby bit is one. if xosc.runstdby is zero, the oscillator is disabled. 0: the oscillator is always on, if enabled. 1: the oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. the oscilla- tor is disabled if no peripheral is requesting the clock source. z bit 6 ? runstdby: run in standby this bit controls how the xosc behaves during standby sleep mode: 0: the oscillator is disabled in standby sleep mode. 1: the oscillator is not stopped in standby sleep mode. if xosc.ondemand is one, the clock source will be run- ning when a peripheral is requesting the clock. if xosc.ondemand is zero, the clock source will always be running in standby sleep mode. z bits 5:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? xtalen: crystal oscillator enable this bit controls the connections between the i/o pads and the external clock or crystal oscillator: 0: external clock connected on xin. xout can be used as general-purpose i/o. 1: crystal connected to xin/xout. table 17-3. external multipurpose crystal oscillator gain settings gain[2:0] recommended max frequency 0x0 2mhz 0x1 4mhz 0x2 8mhz 0x3 16mhz 0x4 30mhz 0x5-0x7 reserved
161 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 z bit 1 ? enable: oscillator enable 0: the oscillator is disabled. 1: the oscillator is enabled. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read.
162 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.6 32khz external crystal oscillator (xosc32k) control name: xosc32k offset: 0x14 reset: 0x0080 property: write-protected z bits 15:13 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 12 ? wrtlock: write lock 0: the generic clock and the associated generic clock generator and division factor using the xosc32k as a clock source are not locked. 1: the generic clock and the associated generic clock generator and division factor using the xosc32k as a clock source are locked. refer to ?gclk ? generic clock controller? on page 83 for details. z bit 11 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 10:8 ? startup[2:0]: oscillator start-up time these bits select the start-up time for the oscillator according to table 17-4 the osculp32k oscillator is used to clock the start-up counter. bit151413121110 9 8 wrtlock startup[2:0] accessrrrrrr/wr/wr/w reset00000000 bit76543210 ondemand runstdby aampen en1k en32k xtalen enable access r/w r/w r/w r/w r/w r/w r/w r reset10000000 table 17-4. start-up time for 32kh z external cryst al oscillator startup[2:0] number of osculp32k clock cycles approximate equivalent time (osculp = 32khz) 0x0 1 32us 0x1 2 64us 0x2 4 128us 0x3 8 256us 0x4 16 512us 0x5 32 1ms 0x6 64 2ms 0x7 128 4ms
163 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 z bit 7 ? ondemand: on demand control the on demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. in on demand operation mode, i.e., if the ondemand bit has been previously written to one, the oscillator will only be running when requested by a peripheral. if there is no peripheral requesting the oscillator?s clock source, the oscillator will be in a disabled state. if on demand is disabled the oscillator will always be running when enabled. in standby sleep mode, the on demand operation is still active if the xosc32k.runstdby bit is one. if xosc32k.runstdby is zero, t he oscillator is disabled. 0: the oscillator is always on, if enabled. 1: the oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. the oscilla- tor is disabled if no peripheral is requesting the clock source. z bit 6 ? runstdby: run in standby this bit controls how the xosc32k behaves during standby sleep mode: 0: the oscillator is disabled in standby sleep mode. 1: the oscillator is not stopped in standby sleep mode. if xosc32k.ondemand is one, the clock source will be running when a peripheral is requesti ng the clock. if xosc32k.ondemand is zero, the clock source will always be running in standby sleep mode. z bit 5 ? aampen: automatic amplitude control enable 0: the automatic amplitude control for the crystal oscillator is disabled. 1: the automatic amplitude control for the crystal oscillator is enabled. z bit 4 ? en1k: 1khz output enable 0: the 1khz output is disabled. 1: the 1khz output is enabled. z bit 3 ? en32k: 32khz output enable 0: the 32khz output is disabled. 1: the 32khz output is enabled. z bit 2 ? xtalen: crystal oscillator enable this bit controls the connections between the i/o pads and the external clock or crystal oscillator: 0: external clock connected on xin32. xout32 can be used as general-purpose i/o. 1: crystal connected to xin32/xout32. z bit 1 ? enable: oscillator enable 0: the oscillator is disabled. 1: the oscillator is enabled. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read.
164 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.7 32khz internal osc illator (osc32k) control name: osc32k offset: 0x18 reset: 0x00000080 property: write-protected z bits 31:23 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 22:16 ? calib[6:0]: oscillator calibration these bits control the oscillator calibration. this value must be written by the user. factory calibration values can be loaded from the non-volatile memory. refer to ?non-volatile memory (nvm) user row mapping? on page 25 . z bits 15:13 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 12 ? wrtlock: write lock 0: the generic clock and the associated generic clock generat or and division factor using the osc32k as clock source are not locked. 1: the generic clock and the associated generic clock generat or and division factor using the osc32k as clock source are locked. refer to ?gclk ? generic clock controller? on page 83 for details. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 calib[6:0] accessr r/wr/wr/wr/wr/wr/wr/w reset00000000 bit151413121110 9 8 wrtlock startup[2:0] access r r r r r r/w r/w r/w reset00000000 bit76543210 ondemand runstdby en1k en32k enable access r/w r/w r r r/w r/w r/w r reset10000000
165 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 z bit 11 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 10:8 ? startup[2:0]: oscillator start-up time these bits select start-up time for the oscillator according to table 17-5 . the osculp32k oscillator is used as input clock to the startup counter. z bit 7 ? ondemand: on demand control the on demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. in on demand operation mode, i.e., if the ondemand bit has been previously written to one, the oscillator will only be running when requested by a peripheral. if there is no peripheral requesting the oscillator?s clock source, the oscillator will be in a disabled state. if on demand is disabled the oscillator will always be running when enabled. in standby sleep mode, the on demand operation is still active if the osc32k.runstdby bit is one. if osc32k.runstdby is zero, the oscillator is disabled. 0: the oscillator is always on, if enabled. 1: the oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. the oscilla- tor is disabled if no peripheral is requesting the clock source. z bit 6 ? runstdby: run in standby this bit controls how the osc32k behaves during standby sleep mode: 0: the oscillator is disabled in standby sleep mode. 1: the oscillator is not stopped in standby sleep mode. if osc32k.ondemand is one, the clock source will be running when a peripheral is requesting the clock. if osc3 2k.ondemand is zero, the clock source will always be running in standby sleep mode. z bits 5:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 3 ? en1k: 1khz output enable 0: the 1khz output is disabled. 1: the 1khz output is enabled. table 17-5. start-up time for 32khz internal oscillator startup[2:0] number of osculp32k clock cycles approximate equivalent time (osculp= 32 khz) 0x0 0 0 0x1 32 1ms 0x2 2048 64ms 0x3 4096 128ms 0x4 16384 512ms 0x5 32768 1s 0x6 65536 2s 0x7 131072 4s
166 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 z bit 2 ? en32k: 32khz output enable 0: the 32khz output is disabled. 1: the 32khz output is enabled. z bit 1 ? enable: oscillator enable 0: the oscillator is disabled. 1: the oscillator is enabled. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read.
167 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.8 32khz ultra low power internal oscillator (osculp32k) control name: osculp32k offset: 0x1c reset: 0xxx property: write-protected z bit 7 ? wrtlock: write lock 0: the generic clock and the associated generic clock gener ator and division factor using the osculp32k as clock source are not locked. 1: the generic clock and the associated generic clock gener ator and division factor using the osculp32k as clock source are locked. refer to ?gclk ? generic clock controller? on page 83 for details. z bits 6:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 4:0 ? calib[4:0]: oscillator calibration these bits control the oscillator calibration. these bits are loaded from flash calibration at startup. bit76543210 wrtlock calib[4:0] access r r r r/w r/w r/w r/w r/w reset0 0 0xxxxx
168 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.9 8mhz internal oscillator (osc8m) control name: osc8m offset: 0x20 reset: 0x0xxx0082 property: write-protected z bits 31:30 ? frange[1:0]: o scillator frequency range these bits control the oscillator frequency range according to table 17-6 . z bits 29:28 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 27:16 ? calib[11:0]: oscillator calibration these bits control the oscillator calibrati on. the calibration field is split in two: bit3130292827262524 frange[1:0] calib[11:8] accessr/wr/w r r r/wr/wr/wr/w reset0000xxxx bit2322212019181716 calib[7:0] accessr/wr/wr/wr/wr/wr/wr/wr/w resetxxxxxxxx bit151413121110 9 8 presc[1:0] accessrrrrrrr/wr/w reset00000000 bit76543210 ondemand runstdby enable access r/w r/w r r r r r/w r reset10000010 table 17-6. oscillator frequency range frange[1:0] description 0x0 4 to 6mhz 0x1 6 to 8mhz 0x2 8 to 11mhz 0x3 11 to 15mhz
169 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 calib[11:7] is for temperature calibration calib[6:0] is for overall process calibration these bits are loaded from flash calibration at startup. z bits 15:10 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 9:8 ? presc[1:0]: oscillator prescaler these bits select the oscillator prescaler factor setting according to the table 17-7 table. z bit 7 ? ondemand: on demand control the on demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. in on demand operation mode, i.e., if the ondemand bit has been previously written to one, the oscillator will only be running when requested by a peripheral. if there is no peripheral requesting the oscillator?s clock source, the oscillator will be in a disabled state. if on demand is disabled the oscillator will always be running when enabled. in standby sleep mode, the on demand operation is still active if the osc8m.runstdby bit is one. if osc8m.runstdby is zero, the oscillator is disabled. 0: the oscillator is always on, if enabled. 1: the oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. the oscilla- tor is disabled if no peripheral is requesting the clock source. z bit 6 ? runstdby: run in standby this bit controls how the osc8m behaves during standby sleep mode: 0: the oscillator is disabled in standby sleep mode. 1: the oscillator is not stopped in standby sleep mode. if osc8m.ondemand is one, the clock source will be run- ning when a peripheral is requesting the clock. if osc8 m.ondemand is zero, the clock source will always be running in standby sleep mode. z bits 5:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? enable: oscillator enable 0: the oscillator is disabled. 1: the oscillator is enabled. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. table 17-7. oscill ator prescaler presc[1:0] description 0x0 1 0x1 2 0x2 4 0x3 8
170 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.10 dfll48m control name: dfllctrl offset: 0x24 reset: 0x0080 property: write-protected z bits 15:10 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 9 ? qldis: quick lock disable 0: quick lock is enabled. 1: quick lock is disabled. z bit 8 ? ccdis: chill cycle disable 0: chill cycle is enabled. 1: chill cycle is disabled. z bit 7 ? ondemand: on demand control the on demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. in on demand operation mode, i.e., if the ondemand bit has been previously written to one, the oscillator will only be running when requested by a peripheral. if there is no peripheral requesting the oscillator?s clock source, the oscillator will be in a disabled state. if on demand is disabled the oscillator will always be running when enabled. in standby sleep mode, the on demand operation is still active if the dfllctrl.runstdby bit is one. if dfllctrl.runstdby is zero, the oscillator is disabled. 0: the oscillator is always on, if enabled. 1: the oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. the oscilla- tor is disabled if no peripheral is requesting the clock source. z bit 6 ? runstdby: run in standby this bit controls how the dfll behaves during standby sleep mode: 0: the oscillator is disabled in standby sleep mode. 1: the oscillator is not stopped in standby sleep mode. if dfllctrl.ondemand is one, the clock source will be running when a peripheral is requesting the clock. if dfllc trl.ondemand is zero, the clock source will always be running in standby sleep mode. bit151413121110 9 8 qldis ccdis accessrrrrrrr/wr/w reset00000000 bit76543210 ondemand runstdby llaw stable mode enable access r/w r/w r r/w r/w r/w r/w r reset10000000
171 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 z bit 5 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 4 ? llaw: lose lock after wake 0: locks will not be lost after waking up from sleep modes if the dfll clock has been stopped. 1: locks will be lost after waking up from sleep modes if the dfll clock has been stopped. z bit 3 ? stable: stable dfll frequency 0: fine calibration tracks changes in output frequency. 1: fine calibration register value will be fixed after a fine lock. z bit 2 ? mode: operating mode selection 0: the dfll operates in open-loop operation. 1: the dfll operates in closed-loop operation. z bit 1 ? enable: dfll enable 0: the dfll oscillator is disabled. 1: the dfll oscillator is enabled. due to synchronization, there is delay from updating the register until the peripheral is enabled/disabled. the value written to dfllctrl.enable will read back immediately after written. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read.
172 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.11 dfll48m value name: dfllval offset: 0x28 reset: 0x00000000 property: write-protected z bits 31:16 ? diff: multiplication ratio difference in closed-loop mode (dfllctrl.mode is written to one), th is bit group indicates the difference between the ideal number of dfll cycles and the counted number of cycles. this value is not updated in open-loop mode, and should be considered invalid in that case. z bits 15:13 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 12:8 ? coarse: coarse value set the value of the coarse calibration register. in closed-loop mode, this field is read-only. z bits 7:0 ? fine: fine value set the value of the fine calibration register. in closed-loop mode, this field is read-only. bit3130292827262524 diff[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit2322212019181716 diff[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit151413121110 9 8 coarse[4:0] access r r r r/w r/w r/w r/w r/w reset00000000 bit76543210 fine[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
173 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.12 dfll48m multiplier name: dfllmul offset: 0x2c reset: 0x00000000 property: write-protected z bits 31:29 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 28:24 ? cstep: coarse maximum step this bit group indicates the maximum step size allow ed during coarse adjustment in closed-loop mode. when adjusting to a new frequency, the expected output frequency overshoot depends on this step size. z bits 23:16 ? fstep: fine maximum step this bit group indicates the maximum step size allow ed during fine adjustment in closed-loop mode. when adjust- ing to a new frequency, the expected output frequency overshoot depends on this step size. z bits 15:0 ? mul: dfll multiply factor this field determines the ratio of the clk_dfll output frequency to the clk_dfll_ref input frequency. writing to the mul register will cause locks to be lost and the fine calibration value to be reset to its midpoint. bit3130292827262524 cstep[4:0] access r r r r/w r/w r/w r/w r/w reset00000000 bit2322212019181716 fstep[7:0] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000 bit151413121110 9 8 mul[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 mul[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
174 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.13 dfll48m synchronization name: dfllsync offset: 0x30 reset: 0x00 property: write-protected z bit 7 ? readreq: read request to be able to read the current value of dfllval in cl osed-loop mode, this bit should be written to one. the updated value is available in dfllval when pclksr.dfllrdy is set. z bits 6:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. bit76543210 readreq accesswrrrrrrr reset00000000
175 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.14 3.3v brown-out de tector (bod33) control name: bod33 offset: 0x34 reset: 0x00xx00xx property: synchronized, write-protected z bits 31:22 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 21:16 ? level[5:0] : bod33 threshold level this field sets the triggering voltage threshold for the bod33. note that any change to the level field of the bod33 register should be done when the bod33 is disabled in order to avoid spurious resets or interrupts. these bits are loaded from flash user row at startup. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details. z bits 15:12 ? psel[3:0]: prescaler select selects the prescaler divide-by output for the bod33 sampling mode, as given in table 17-8 . the input clock comes from the osculp32k 1khz output. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 level[5:0] access r r r/w r/w r/w r/w r/w r/w reset0 0xxxxxx bit151413121110 9 8 psel[3:0] cen mode access r/w r/w r/w r/w r r r/w r/w reset00000000 bit76543210 runstdby action[1:0] hyst enable access r r/w r r/w r/w r/w r/w r reset000xx0x0
176 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 z bits 11:10 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 9 ? cen: clock enable 0: the bod33 sampling clock is either disabled and stopped, or enabled but not yet stable. 1: the bod33 sampling clock is either enabled and stable, or disabled but not yet stopped. writing a zero to this bit will stop the bod33 sampling clock. writing a one to this bit will start the bod33 sampling clock. z bit 8 ? mode: operation mode 0: the bod33 operates in continuous mode. 1: the bod33 operates in sampling mode. z bit 7 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 6 ? runstdby: run in standby 0: the bod33 is disabled in standby sleep mode. 1: the bod33 is enabled in standby sleep mode. z bit 5 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. table 17-8. bod33 prescaler select psel[3:0] name description 0x0 div2 divide clock by 2 0x1 div4 divide clock by 4 0x2 div8 divide clock by 8 0x3 div16 divide clock by 16 0x4 div32 divide clock by 32 0x5 div64 divide clock by 64 0x6 div128 divide clock by 128 0x7 div256 divide clock by 256 0x8 div512 divide clock by 512 0x9 div1k divide clock by 1024 0xa div2k divide clock by 2048 0xb div4k divide clock by 4096 0xc div8k divide clock by 8192 0xd div16k divide clock by 16384 0xe div32k divide clock by 32768 0xf div64k divide clock by 65536
177 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 z bits 4:3 ? action: bod33 action these bits are used to select the bod33 action when the supply voltage crosses below the bod33 threshold, as shown in table 17-9 . these bits are loaded from flash user row at startup. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details. z bit 2 ? hyst: hysteresis this bit indicates whether hysteresis is enabled for the bod33 threshold voltage: 0: no hysteresis. 1: hysteresis enabled. z bit 1 ? enable: enable 0: bod33 is disabled. 1: bod33 is enabled. this bit is loaded from flash user row at startup. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. table 17-9. bod33 action action[1:0] name description 0x0 none no action 0x1 reset the bod33 generates a reset 0x2 interrupt the bod33 generates an interrupt 0x3 - reserved
178 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.15 1.2v brown-out de tector (bod12) control name: bod12 offset: 0x38 reset: 0x00xx00xx property: synchronized, write-protected z bits 31:21 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 20:16 ? level[4:0] : bod12 threshold level this field sets the triggering voltage threshold for the bod12. note that any change to the level field of the bod12 register should be done when the bod12 is disabled in order to avoid spurious resets or interrupts. these bits are loaded from flash user row at startup. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details. z bits 15:12 ? psel[3:0]: prescaler select selects the prescaler divide-by output for the bod12 sampling mode, as given in table 17-10 . the input clock comes from the osculp32k 1khz output. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 level[4:0] access r r r r/w r/w r/w r/w r/w reset0 0 0xxxxx bit151413121110 9 8 psel[3:0] cen mode access r/w r/w r/w r/w r r r/w r/w reset00000000 bit76543210 runstdby action[1:0] hyst enable access r r/w r r/w r/w r/w r/w r reset000xx0x0
179 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 z bits 11:10 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 9 ? cen: clock enable 0: the bod12 sampling clock is either disabled and stopped, or enabled but not yet stable. 1: the bod12 sampling clock is either enabled and stable, or disabled but not yet stopped. writing a zero to this bit will stop the bod12 sampling clock. writing a one to this bit will start the bod12 sampling clock. z bit 8 ? mode: operation mode 0: the bod12 operates in continuous mode. 1: the bod12 operates in sampling mode. z bit 7 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 6 ? runstdby: run in standby 0: the bod12 is disabled in standby sleep mode. 1: the bod12 is enabled in standby sleep mode. z bit 5 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. table 17-10. bod12 prescaler select psel[3:0] name description 0x0 div2 divide clock by 2 0x1 div4 divide clock by 4 0x2 div8 divide clock by 8 0x3 div16 divide clock by 16 0x4 div32 divide clock by 32 0x5 div64 divide clock by 64 0x6 div128 divide clock by 128 0x7 div256 divide clock by 256 0x8 div512 divide clock by 512 0x9 div1k divide clock by 1024 0xa div2k divide clock by 2048 0xb div4k divide clock by 4096 0xc div8k divide clock by 8192 0xd div16k divide clock by 16384 0xe div32k divide clock by 32768 0xf div64k divide clock by 65536
180 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 z bits 4:3 ? action: bod12 action these bits are used to select the bod12 action when the supply voltage crosses below the bod12 threshold, as shown in table 17-11 . these bits are loaded from flash user row at startup. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details. z bit 2 ? hyst: hysteresis this bit indicates whether hysteresis is enabled for the bod12 threshold voltage: 0: no hysteresis. 1: hysteresis enabled. z bit 1 ? enable: enable 0: bod12 is disabled. 1: bod12 is enabled. this bit is loaded from flash user row at startup. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. table 17-11. bod12 action action[1:0] name description 0x0 none no action 0x1 reset the bod12 generates a reset 0x2 interrupt the bod12 generates an interrupt 0x3 - reserved
181 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.16 voltage regulator system (vreg) control name: vreg offset: 0x3c reset: 0x0x02 property: write protected z bit 15 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 14:12 ? calib[2:0]: voltage regulator calibration these bits are used for voltage regulator calibration. z bit 11 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 10:8 ? level[2:0]: voltage regulator level these bits are used to set the voltage level of the regulator . these bits are loaded from flash calibration row at startup. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details z bit 7 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 6 ? runstdby: run in standby 0: the voltage regulator is in low-power configuration in standby sleep mode. 1: the voltage regulator is not in low-power configuration in standby sleep mode. z bits 5:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? enable: enable 0: the voltage regulator is disabled. 1: the voltage regulator is enabled. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. bit151413121110 9 8 calib[2:0] level[2:0] access r r/w r/w r/w r r/w r/w r/w reset 0 0 0 0 0 x x x bit 7 6 5 4 3 2 1 0 runstdby enable access r r/w r r r r r/w r reset 0 0 0 0 0 0 1 0
182 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 17.8.17 voltage references system (vref) control name: vref offset: 0x40 reset: 0x0xxx0000 property: write-protected z bits 31:27 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 26:16 ? calib[10:0]: bandgap voltage generator calibration these bits are used to calibrate the output level of the bandgap voltage reference. these bits are loaded from flash calibration row at startup. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details. z bits 15:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? bgouten: bandgap output enable 0: the bandgap output is not available as an adc input channel. 1: the bandgap output is routed to an adc input channel. z bit 1 ? tsen: temper ature sensor enable 0: temperature sensor is disabled. bit3130292827262524 calib[10:8] accessrrrrrr/wr/wr/w reset00000xxx bit2322212019181716 calib[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w resetxxxxxxxx bit151413121110 9 8 accessrrrrrrrr reset00000000 bit76543210 bgouten tsen accessrrrrrr/wr/wr reset00000000
183 atmel sam d20 [preliminary datasheet] 42129a??sam??06/2013 1: temperature sensor is enabled and routed to an adc input channel. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read.
184 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18. wdt ? watchdog timer 18.1 overview the watchdog timer (wdt) is a system function for monitoring correct program operation. it makes it possible to recover from error situations such as runaway or deadlocked code. the wdt is configured to a predefined time-out period, and is constantly running when enabled. if the wdt is not cleared within the time-out period, it will issue a system reset. an early-warning interrupt is available to indi cate an upcoming watchdog time-out condition. the window mode makes it possible to define a time slot (or window) inside the total time-out period during which the wdt must be cleared. if the wdt is cleared outside this window , either too early or too late, a system reset will be issued. compared to the normal mode, this can also catch situations where a code error causes the wdt to be cleared frequently. when enabled, the wdt will run in active mode and all sleep modes. it is asynchronous and runs from a cpu- independent clock source.the wdt will continue operation and issue a system reset or interrupt even if the main clocks fail. 18.2 features z issues a system reset if the watchdog timer is not cleared before its time-out period z early warning interrupt generation z asynchronous operation from dedicated oscillator z two types of operation: z normal mode z window mode z selectable time-out periods, from 8 cycles to 16,000 cycles in normal mode or 16 cycles to 32,000 cycles in window mode z always-on capability 18.3 block diagram figure 18-1. wdt block diagram gclk_wdt count reset per/window/ewoffset 0 clear 0xa5 early warning interrupt
185 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18.4 signal description not applicable. 18.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 18.5.1 i/o lines not applicable. 18.5.2 power management the wdt can continue to operate in any sleep mode where the selected source clock is running. the wdt interrupts can be used to wake up the device from sleep modes. the events can trigger other operations in the system without exiting sleep modes. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. 18.5.3 clocks the wdt bus clock (clk_wdt_apb) is enabled by defau lt, and can be enabled and disabled in the power manager. refer to ?pm ? power manager? on page 105 for details. a generic clock (gclk_wdt) is required to clock the wdt. this clock must be configured and enabled in the generic clock controller before using the wdt. refer to ?gclk ? generic clock controller? on page 83 for details. this generic clock is asynchronous to the user interface cl ock (clk_wdt_apb). due to this asynchronicity, accessing certain registers will require synchronization between the clock domains. refer to ?synchronization? on page 189 for further details. gclk_wdt is intended to be sourced from the clock of the in ternal ultra-low-power (ulp) oscillator. due to the ultra- low-power design, the oscillator is not very accurate, and so the exact time-out period may vary from device to device. this variation must be kept in mind when designing software t hat uses the wdt to ensure that the time-out periods used are valid for all devices. gclk_wdt can also be clocked from other sources if a more accurate clock is needed, but at the cost of higher power consumption. 18.5.4 dma not applicable. 18.5.5 interrupts the interrupt request line is connected to the interrupt c ontroller. using the wdt interrupts requires the interrupt controller to be configured first. refer to ?nested vector interrupt controller? on page 28 for details. 18.5.6 events not applicable. 18.5.7 debug operation when the cpu is halted in debug mode, the wdt will halt normal operation. if the wdt is configured in a way that requires it to be periodically serviced by the cpu through inte rrupts or similar, improper operation or data loss may result during debugging. the wdt can be forced to halt operation during debugging. 18.5.8 register access protection all registers with write-access are optionally write-protect ed by the peripheral access controller (pac), except the following registers:
186 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z interrupt flag status and clear register (intflag) write-protection is denoted by the write-protection property in the register description. when the cpu is halted in debug mode, all wr ite-protection is automatically disabled. write-protection does not apply for accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details. 18.5.9 analog connections not applicable. 18.6 functional description 18.6.1 principle of operation the watchdog timer (wdt) is a system for monitoring correct program operation, making it possible to recover from error situations such as runaway code by issuing a reset. when enabled, the wdt is a constantly running timer that is configured to a predefined time-out period. before the e nd of the time-out period, the wdt should be reconfigured. the wdt has two modes of operation, normal and window. addi tionally, the user can enable early warning interrupt generation in each of the modes. the description for each of the basic modes is given below. the settings in the control register (ctrl) and the interrupt enable register (intenclr/ set) determine the mode of operation, as illustrated in table 18-1 . 18.6.2 basic operation 18.6.2.1 initialization the following registers are enable-protected: z control register (ctrl), except the enable bit (ctrl.enable) z configuration register (config) z early warning interrupt control register (ewctrl) any writes to these bits or registers when the wdt is enabled or is being enabled (ctrl.enable is one) will be discarded. writes to these registers while the wdt is being disabled will be completed after the disabling is complete. enable-protection is denoted by the enable-protected property in the register description. initialization of the wdt can be done only while the wdt is disabled. the wdt is configured by defining the required time-out period bits in the configuration register (c onfig.per). if window-mode operation is required, the window enable bit in the control register (ctrl.wen) must be writ ten to one and the window period bits in the configuration register (config.window) must be defined. table 18-1. wdt operating modes enable wen interrupt enable mode 0 x x stopped 1 0 0 normal 1 0 1 normal with early warning interrupt 1 1 0 window 1 1 1 window with early warning interrupt
187 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18.6.2.2 configurable reset values on a power-on reset, some registers will be loaded with initial values from the nvm user row. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details. this encompasses the following bits and bit groups: z enable bit in the control register (ctrl.enable) z always-on bit in the contro l register (ctrl.alwayson) z watchdog timer windows mode enable bit in the control register (ctrl.wen) z watchdog timer windows mode time-out period bits in the configuration register (config.window) z time-out period in the configuration register (config.per) z early warning interrupt time offset bits in the earl y warning interrupt control register (ewctrl.ewoffset) for more information about fuse locations, see ?non-volatile memory (nvm) user row mapping? on page 25 . 18.6.2.3 enabling and disabling the wdt is enabled by writing a one to the enable bit in the control register (ctrl.enable). the wdt is disabled by writing a zero to ctrl.enable. the wdt can be disabled only while the always-on bit in the control register (ctrl.alwayson) is zero. 18.6.2.4 normal mode in normal-mode operation, the length of a time-out period is configured in config.per. the wdt is enabled by writing a one to the enable bit in the control register (ctrl.enab le). once enabled, if the wdt is not cleared from the application code before the time-out occurs, the wdt will issue a system reset. there are 12 possible wdt time-out (to wdt ) periods, selectable from 8ms to 16s, and the wdt can be cleared at any time during the time-out period. a new wdt time-out period will be started each time the wdt is cleared by writing 0xa5 to the clear register (clear). writing any value other than 0xa5 to clear will issue an immediate system reset. by default, wdt issues a system reset upon a time-out, and the early warning interrupt is disabled. if an early warning interrupt is required, the early warning interrupt enable bi t in the interrupt enable register (intenset.ew) must be enabled. writing a one to the early warning interrupt bit in the interrupt enable set register (intenset.ew) enables the interrupt, and writing a one to the early warning interrupt bit in the interrupt enable clear register (intenclr.ew) disables the interrupt. if the early warning interrupt is enabled, an interrupt is generated prior to a watchdog time-out condition. in normal mode, the early warning offset bi ts in the early warning interrupt control register (ewctrl.ewoffset) define the time where the early warning interrupt occurs. the normal-mode operation is illustrated in figure 18-2 . figure 18-2. normal-mode operation t [ms] wdt count 510 15 20 25 30 35 per[3:0]=1 timely wdt clear to wdt wdt timeout system reset ewoffset[3:0]=0 early warning interrupt
188 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18.6.2.5 window mode in window-mode operation, the wdt uses two different ti me-out periods, a closed window time-out period (to wdtw ) and the normal, or open, time-out period (to wdt ). the closed window time-out period defines a duration from 8ms to 16s where the wdt cannot be reset. if the wdt is cleared during this period, the wdt will issue a system reset. the normal wdt time-out period, which is also from 8ms to 16s, defines the duration of the open period during which the wdt can be cleared. the open period will always follow the closed period, and so the total duration of the time-out period is the sum of the closed window and the open window time-out peri ods. the closed window is defined by the window period bits in the configuration register (config.window), and the open window is defined by the period bits in the configuration register (config.per). by default, the wdt issues a system reset upon a time-out and the early warning interrupt is disabled. if an early warning interrupt is required, intenclr/set.ew must be set. writing a one to inte nset.ew enables the interrupt, and writing a one to intenclr.ew disables the interrupt. if the early warning interrupt is enabled in window mode, the interrupt is generated at the start of the open window period. the window mode operation is illustrated in figure 18-3 . figure 18-3. window-mode operation 18.6.3 additional features 18.6.3.1 always-on mode the always-on mode is enabled by writing a one to the always-o n bit in the control register (ctrl.alwayson). when the always-on mode is enabled, the wdt runs continuously, regardless of the state of ctrl.enable. once written, the always-on bit can only be cleared by a power-on reset. the configuration (config) and early warning control (ewctrl) registers are read-only register s while the ctrl.alwayson bit is set. thus, the time period configuration bits (config.per, config.window, ewctrl .ewoffset) of the wdt cannot be changed. enabling or disabling window-mode operati on by writing the window enable bit (c trl.wen) is allowed while in the always-on mode, but note that config.per cannot be changed. the interrupt clear and interrupt set registers are accessible in the always-on mode. the early warning interrupt can still be enabled or disabled while in the always-on mode, but note that ewctrl.ewoffset cannot be changed. table 18-2 shows the operation of the wdt when ctrl.alwayson is set. t [ms] wdt count 510 15 20 25 30 35 window[3:0]=0 per[3:0]=0 timely wdt clear closed to wdtw open to wdt early wdt clear wdt timeout early warning interrupt
189 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 18-2. wdt operating modes with always-on 18.6.4 interrupts the wdt has the following interrupt sources: z early warning each interrupt source has an interrupt flag associated with i t. the interrupt flag in the interrupt flag status and clear register (intflag) is set when the interrupt condition occu rs. each interrupt can be individually enabled by writing a one to the corresponding bit in the interrupt enable set regi ster (intenset), and disabled by writing a one to the corresponding bit in the interrupt enable clear register (int enclr). an interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the wdt is reset. see intflag for details on how to clear interrupt flags. the wdt has one common interrupt request line for all the inte rrupt sources. the user mu st read intflag to determine which interrupt condition is present. note that interrupts must be globally enabled for interrupt requests to be generated. refer to ?nested vector interrupt controller? on page 28 for details. the early warning interrupt behaves differently in normal mode and in window mode. in normal mode, the early warning interrupt generation is defined by the early warning offset in the early warning control register (ewctrl.ewoffset). the early warning offset bits define the number of gclk_wdt clocks before the interrupt is generated, relative to the start of the watchdog time-out period. for example, if the wdt is operating in normal mode with config.per = 0x2 and ewctrl.ewoffset = 0x1, the early warning interrupt is generated 16 gclk_wdt clock cycles from the start of the watchdog time-out period, and the watchdog time-out system reset is generated 32 gclk_wdt clock cycles from the start of the watchdog time-out period. the user must take caution when programming the early warning offset bits. if these bits define an early warning interrupt generation time greater than the watchdog time-out period, the watchdog time-out system reset is generated prior to the early warning interrupt. thus, the early warning interrupt will never be generated. in window mode, the early warning interrupt is generated at the start of the open window period. in a typical application where the system is in sleep mode, it can use this interrupt to wake up and clear the watchdog timer, after which the system can perform other tasks or return to sleep mode. 18.6.5 synchronization due to the asynchronicity between clk_wdt_apb and gclk_wdt some registers must be synchronized when accessed. a register can require: z synchronization when written z synchronization when read z synchronization when written and read z no synchronization when executing an operation that requires synchronization, the synchronization busy bit in the status register(status.syncbusy) will be set immediately, and cleared when synchronization is complete. the synchronization ready interrupt can be used to signal when sync is complete. this can be accessed via the synchronization ready interrupt flag in the interrupt flag status and clear register (intflag.syncrdy). wen interrupt enable mode 0 0 always-on and normal mode 0 1 always-on and normal mode with early warning interrupt 1 0 always-on and window mode 1 1 always-on and window mode with early warning interrupt
190 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 if an operation that requires synchronization is executed wh ile status.syncbusy is one, the bus will be stalled. all operations will complete successfully, but the cpu will be stalled and interrupts will be pending as long as the bus is stalled. the following registers need synchronization when written: z control register (ctrl) z clear register (clear) write-synchronization is denoted by the write-synchronized property in the register description.
191 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18.7 register summary register summary offset name bit pos. 0x0 ctrl 7:0 alwayson wen enable 0x1 config 7:0 window[3:0] per[3:0] 0x2 ewctrl 7:0 ewoffset[3:0] 0x3 reserved 0x4 intenclr 7:0 ew 0x5 intenset 7:0 ew 0x6 intflag 7:0 ew 0x7 status 7:0 syncbusy 0x8 clear 7:0 clear[7:0]
192 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each individual register description. please refer to ?register access protection? on page 185 for details. some registers require synchronization when read and/or wr itten. synchronization is denoted by the write-synchronized or the read-synchronized property in each indi vidual register description. please refer to ?synchronization? on page 189 for details. some registers are enable-protected, meaning they can be wr itten only when the wdt is disabled. enable-protection is denoted by the enable-protected property in each individual register description.
193 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18.8.1 control name: ctrl offset: 0x0 reset: n/a - loaded from nvm user row at startup property: write-protected, enable-protected, write-synchronized z bit 7 ? alwayson: always-on this bit allows the wdt to run continuously. after being written to one, this bit cannot be written to zero, and the wdt will remain enabled until a power-on reset is received. w hen this bit is one, the control register (ctrl), the configuration register (config) and the early warni ng control register (ewctrl) will be read-only, and any writes to these registers are not allowed. writing a zero to this bit has no effect. 0: the wdt is enabled and disabled through the enable bit. 1: the wdt is enabled and can only be disabled by a power-on reset (por). this bit is not enable-protected. these bits are loaded from nvm user row at startup. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details. z bits 6:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? wen: watchdog timer window mode enable this bit enables window mode. can be written only while ctrl.alwayson is zero. the initial value of this bit is loaded from flash calibration . 0: window mode is disabled (normal operation). 1: window mode is enabled. this bit is loaded from nvm user row at startup. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details. z bit 1 ? enable: enable this bit enables or disables the wdt. can only be written while ctrl.alwayson is zero. 0: the wdt is disabled. 1: the wdt is enabled. due to synchronization, there is delay from writing ctrl.enable until the peripheral is enabled/disabled. the value written to ctrl.enable will read back immediately, and the synchronization busy bit in the status register (status.syncbusy) will be set. status.syncbusy will be cleared when the operation is complete. this bit is not enable-protected. this bit is loaded from nvm user row at startup. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. bit76543210 alwayson wen enable access r/w1 r/w r/w r/w r/w r/w r/w r/w resetx0000xx0
194 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18.8.2 configuration name: config offset: 0x1 reset: n/a - loaded from nvm user row at startup property: write-protected, enable-protected, write-synchronized z bits 7:4 ? window[3:0]: window mode time-out period in window mode, these bits determine the watchdog closed window period as a number of oscillator cycles. the closed window periods are defined in table 18-3 . these bits are loaded from nvm user row at startup. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details. z bits 3:0 ? per[3:0]: time-out period these bits determine the watchdog time-out period as a number of gclk_wdt clock cycles. in window mode operation, these bits define the open window period. the different typical time-out periods are found in table 18-4 . these bits are loaded from nvm user row at startup. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details. bit76543210 window[3:0] per[3:0] access r/w r/w r/w r/w r/w r/w r/w r/w resetxxxxxxxx table 18-3. window mode time-out period value description 0x0 8 clock cycles 0x1 16 clock cycles 0x2 32 clock cycles 0x3 64 clock cycles 0x4 128 clock cycles 0x5 256 clocks cycles 0x6 512 clocks cycles 0x7 1024 clock cycles 0x8 2048 clock cycles 0x9 4096 clock cycles 0xa 8192 clock cycles 0xb 16384 clock cycles 0xc-0xf reserved
195 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 18-4. time-out period value description 0x0 8 clock cycles 0x1 16 clock cycles 0x2 32 clock cycles 0x3 64 clock cycles 0x4 128 clock cycles 0x5 256 clocks cycles 0x6 512 clocks cycles 0x7 1024 clock cycles 0x8 2048 clock cycles 0x9 4096 clock cycles 0xa 8192 clock cycles 0xb 16384 clock cycles 0xc-0xf reserved
196 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18.8.3 early warning interrupt control name: ewctrl offset: 0x2 reset: n/a - loaded from nvm user row at startup property: write-protected, enable-protected z bits 7:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 3:0 ? ewoffset[3:0]: earl y warning interrupt time offset these bits determine the number of gclk_wdt clocks in th e offset from the start of the watchdog time-out period to when the early warning interrupt is generated. the early warning offset is defined in table 18-5 . these bits are loaded from nvm user row at startup. refer to ?non-volatile memory (nvm) user row mapping? on page 25 for more details. bit76543210 ewoffset[3:0] acces s rrrrr/wr/wr/wr/w reset0 0 0 0xxxx table 18-5. early warning interrupt time offset value description 0x0 8 clock cycles 0x1 16 clock cycles 0x2 32 clock cycles 0x3 64 clock cycles 0x4 128 clock cycles 0x5 256 clocks cycles 0x6 512 clocks cycles 0x7 1024 clock cycles 0x8 2048 clock cycles 0x9 4096 clock cycles 0xa 8192 clock cycles 0xb 16384 clock cycles 0xc-0xf reserved
197 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18.8.4 interrupt enable clear this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable set register (intenset). name: intenclr offset: 0x4 reset: 0x00 property: write-protected z bits 7:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? ew: early warning interrupt enable 0: the early warning interrupt is disabled. 1: the early warning interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit disables the early warning interrupt. bit76543210 ew accessrrrrrrrr/w reset00000000
198 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18.8.5 interrupt enable set this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear register (intenclr). name: intenset offset: 0x5 reset: 0x00 property: write-protected z bits 7:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? ew: early warning interrupt enable 0: the early warning interrupt is disabled. 1: the early warning interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit enables the early warning interrupt. bit76543210 ew accessrrrrrrrr/w reset00000000
199 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18.8.6 interrupt flag status and clear name: intflag offset: 0x6 reset: 0x00 property: ? z bits 7:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. these bits will always return zero when read. z bit 0 ? ew: early warning this flag is set when an early warning interrupt occurs, as defined in ewctrl .ewoffset. writing a zero to this bit has no effect. writing a one to this bit clears the early warning interrupt flag. bit76543210 ew accessrrrrrrrr/w reset00000000
200 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18.8.7 status name: status offset: 0x7 reset: 0x00 property: ? z bit 7 ? syncbusy: synchronization busy this bit is cleared when the synchronization of registers between clock domains is complete. this bit is set when the synchronization of registers between clock domains is started. z bits 6:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. bit 76543210 syncbusy accessrrrrrrrr reset00000000
201 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18.8.8 clear name: clear offset: offset: 0x8 reset: 0x00 property: write-protected, write-synchronized z bits 7:0 ? clear: watchdog clear writing 0xa5 to this register will clear the watchdog ti mer and the watchdog time-out period is restarted. writing any other value will issue an immediate system reset. bit 76543210 clear[7:0] accesswwwwwwww reset00000000
202 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 18.9 asynchronous watchdog clock characterization the source intended for the asynchronous watchdog clock (osculp32k) has a variance of +/- 15%. in a typical application with gclk_wdt = 1khz or gclk_wdt = 32khz, the time period is illustrated in table 18-6 . table 18-6. typical time-out period typical time-out periods gclk_wdt = 1khz gclk_wdt = 32khz min typ max min typ max 8 clock cycles 6.64ms 7.81ms 8.98ms 0.20ms 0.24ms 0.28ms 16 clock cycles 13.28ms 15.62ms 17.97ms 0.41ms 0.48ms 0.56ms 32 clock cycles 26.56ms 31.25ms 39.94ms 0.83ms 0.97ms 1.12ms 64 clock cycles 53.12ms 62.50ms 71.87ms 1.66ms 1.95ms 2.24ms 128 clock cycles 0.10s 0.12s 0.14s 3.32ms 3.90ms 4.49ms 256 clocks cycles 0.21s 0.25s 0.28s 6.64ms 7.81ms 8.98ms 512 clocks cycles 0.42s 0.50s 0.57s 13.28ms 15.62ms 17.96ms 1024 clock cycles 0.85s 1.00s 1.15s 26.56ms 31.25ms 35.93ms 2048 clock cycles 1.70s 2.00s 2.30s 53.12ms 62.50ms 71.87ms 4096 clock cycles 3.40s 4.00s 4.60s 0.10s 0.12s 0.14s 8192 clock cycles 6.80s 8.00s 9.20s 0.21s 0.25s 0.28s 16384 clock cycles 13.60s 16.00s 18.40s 0.42s 0.50s 0.57s
203 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19. rtc ? real-time counter z 19.1 overview the real-time counter (rtc) is a 32-bit c ounter with a 10-bit programmable prescaler that typically runs continuously to keep track of time. the rtc can wake up the device from sl eep modes using the alarm/compare wake up, periodic wake up or overflow wake up mechanisms. the rtc is typically clocked by the 1.024khz output from the32.768khz high-accuracy internal crystal oscillator(osc32k) and this is the configuration optimized for the lowest power consumption. the faster 32.768khz output can be selected if the rtc needs a resolution higher t han 1ms. the rtc can also be clocked from other sources, selectable through the generic clock module (gclk). the rtc can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare interrupts and peripheral events, which can trigger at any counter value. additionally, the timer can trigger an overflow interrupt and peripheral event, and be reset on the occurrence of an alarm/compare match. this allows periodic interrupts and peripheral events at very long and accurate intervals. the 10-bit programmable prescaler can scale down the cloc k source, and so a wide range of resolutions and time-out periods can be configured. with a 32.768khz clock source, t he minimum counter tick interval is 30.5s, and time-out periods can range up to 36 hours. with the counter tick interval configured to 1s, the maximum time-out period is more than 136 years. 19.2 features z 32-bit counter with 10-bit prescaler z multiple clock sources z 32-bit or 16-bit counter mode z one 32-bit or two 16-bit compare values z clock/calendar mode z time in seconds, minu tes and hours (12/24) z date in day of month, month and year z leap year correction z digital prescaler correction/tuning for increased accuracy z overflow, alarm/compare match and prescaler interrupts and events z optional clear on alarm/compare match 19.3 block diagram figure 19-1. rtc block diagram (mode 0 ? 32-bit counter) count compn = compare n overflow 0 matchclr 10-bit prescaler gclk_rtc clk_rtc_cnt 32 periodic events 32
204 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 19-2. rtc block diagram (mode 1 ? 16-bit counter) figure 19-3. rtc block diagram (mode 2 ? clock/calendar) 19.4 signal description not applicable. 19.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 19.5.1 i/o lines not applicable. 19.5.2 power management the rtc can continue to operate in any sleep mode. the rtc interrupts can be used to wake up the device from sleep modes. the events can trigger other operations in the system without exiting sleep modes. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. the rtc will be reset only at power-on (por) or by writing a one to the software reset bit in the control register (ctrl.swrst). - 10-bit prescaler gclk_rtc count per overflow 0 compn compare n clk_rtc_cnt 16 periodic events 16 16 = = clock alarmn = alarm n overflow 0 matchclr 10-bit prescaler gclk_rtc clk_rtc_cnt 32 periodic events 32 maskn y/m/d h:m:s y/m/d h:m:s
205 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.5.3 clocks the rtc bus clock (clk_rtc_apb) can be enabled and dis abled in the power manager, and the default state of clk_rtc_apb can be found in the peripheral clock masking section in the ?pm ? power manager? on page 105 . a generic clock (gclk_rtc) is required to clock the rtc. this clock must be configured and enabled in the generic clock controller before using the rtc. refer to ?gclk ? generic clock controller? on page 83 for details. this generic clock is asynchronous to the user interface cl ock (clk_rtc_apb). due to this asynchronicity, accessing certain registers will require synchronization between the clock domains. refer to ?synchronization? on page 209 for further details. 19.5.4 dma not applicable. 19.5.5 interrupts the interrupt request line is connected to the interrupt c ontroller. using the rtc interrupts requires the interrupt controller to be configured first. refer to ?nested vector interrupt controller? on page 28 for details. 19.5.6 events to use the rtc event functionality, the corresponding events need to be configured in the event system. refer to ?evsys ? event system? on page 314 for details. 19.5.7 debug operation when the cpu is halted in debug mode the rtc will halt normal operation. the rtc can be forced to continue operation during debugging. refer to the dbgctrl register for details. 19.5.8 register access protection all registers with write-access are optionally write-protect ed by the peripheral access controller (pac), except the following registers: z interrupt flag status and clear register (intflag) z read request register (readreq) z status register (status) z debug register (dbgctrl) write-protection is denoted by the write-protection property in the register description. when the cpu is halted in debug mode, all wr ite-protection is automatically disabled. write-protection does not apply for accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details. 19.5.9 analog connections a 32.768khz crystal can be connected to the tosc1 and tosc2 pins, along with any required load capacitors. 19.6 functional description 19.6.1 principle of operation the rtc keeps track of time in the system and enables periodi c events, as well as interrupts and events at a specified time. the rtc consists of a 10-bit prescaler that feeds a 32-bit counter. the actual forma t of the 32-bit counter depends on the rtc operating mode.
206 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.6.2 basic operation 19.6.2.1 initialization the following bits are enable-protected, meaning that they c an only be written when the rtc is disabled (ctrl.enable is zero): z operating mode bits in the c ontrol register (ctrl.mode) z prescaler bits in the contro l register (ctr l.prescaler) z clear on match bit in the control register (ctrl.matchclr) z clock representation bit in the control register (ctrl.clkrep) the following register is enable-protected: z event control register (evctrl) any writes to these bits or registers when the rtc is enabl ed or being disabled (ctrl.enable is one) will be discarded. writes to these bits or registers while the rtc is being disabled will be completed after the disabling is complete. enable-protection is denoted by the enable-prot ection property in the register description. before the rtc is enabled, it must be configured, as outlined by the following steps: z rtc operation mode must be selected by writing the operating mode bit group in the control register (ctrl.mode) z clock representation must be selected by writing the clock representation bit in the control register (ctrl.clkrep) z prescaler value must be selected by writing the presca ler bit group in the control register (ctrl.prescaler) the rtc prescaler divides down the source clock for the rtc counter. the frequency of the rtc clock (clk_rtc_cnt) is given by the following formula: the frequency of the generic clock, gclk_rtc, is given by f gclk_rtc , and f clk_rtc_cnt is the frequency of the internal prescaled rtc clock, clk_rtc_cnt. note that in the clock/calendar mode, the prescaler must be configured to provide a 1hz clock to the counter for correct operation. 19.6.2.2 enabling, disabling and resetting the rtc is enabled by writing a one to the enable bit in the control register (ctrl.enable). the rtc is disabled by writing a zero to ctrl.enable. the rtc should be disabled before resetting it. the rtc is reset by writing a one to the software reset bit in the control register (ctrl.swrst). all registers in the rtc, except dbgctrl, will be reset to their initial state, and the rtc will be disabled. refer to the ctrl register for details. 19.6.3 operating modes the rtc counter supports three rtc operating modes: 32-bit counter, 16-bit counter and clock/calendar. the operating mode is selected by the operating mode bi t group in the control register (ctrl.mode). 19.6.3.1 32-bit counter (mode 0) when the rtc operating mode bits in the control register (ctrl.mode) are zero, the counter operates in 32-bit counter mode. the block diagram of this mode is shown in figure 19-1 . when the rtc is enabled, the counter will increment on every 0-to-1 transition of clk_rtc_cnt. the counter will increment until it reaches the top value of f clk_rtc_cnt f gclk_rtc 2 prescaler ----------------------------- =
207 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 0xffffffff, and then wrap to 0x00000000. this sets the overflow interrupt flag in the interrupt flag status and clear register (intflag.ovf). the rtc counter value can be read from or written to the counter value register (count) in 32-bit format. the counter value is continuously compared with the 32-bit compare register (comp0). when a compare match occurs, the compare 0interrupt flag in the interrupt flag status and clear register (intflag.cmp0) is set on the next 0-to-1 transition of clk_rtc_cnt. if the clear on match bit in the control register (ctrl.ma tchclr) is one, the counter is cleared on the next counter cycle when a compare match with comp0 occurs. this allows the rtc to generate periodic interrupts or events with longer periods than are possible with the prescaler event s. note that when ctrl.matchclr is one, intflag.cmp0 and intflag.ovf will both be set simultaneously on a compare match with comp0. 19.6.3.2 16-bit counter (mode 1) when ctrl.mode is one, the counter operates in 16-bit counter mode as shown in figure 19-2 . when the rtc is enabled, the counter will increment on every 0-to-1 transi tion of clk_rtc_cnt. in 16-bit counter mode, the 16-bit period register (per) holds the maximum value of the counter. the counter will increment until it reaches the per value, and then wrap to 0x0000. this sets the overflow interrupt flag in the interrupt flag status and clear register (intflag.ovf). the rtc counter value can be read from or written to the counter value register (count) in 16-bit format. the counter value is continuously compared with the 16-bit compare registers (c ompn, n=0?1). when a compare match occurs, the compare n interrupt flag in the interrupt flag status and clear register (intflag.cmpn, n=0?1) is set on the next 0-to-1 transition of clk_rtc_cnt. 19.6.3.3 clock/calendar (mode 2) when ctrl.mode is two, the counter operates in clock/calendar mode, as shown in figure 19-3 . when the rtc is enabled, the counter will increment on every 0-to-1 transi tion of clk_rtc_cnt. the selected clock source and rtc prescaler must be configured to provide a 1hz clock to the counter for correct operation in this mode. the time and date can be read from or written to the clock val ue register (clock) in a 32-bit time/date format. time is represented as: z seconds z minutes z hours hours can be represented in either 12- or 24-hour format, select ed by the clock representation bit in the control register (ctrl.clkrep). this bit can be changed only while the rtc is disabled. date is represented as: z day as the numeric day of the month (starting at 1) z month as the numeric month of the year (1 = january, 2 = february, etc.) z year as a value counting the offset from a reference value that must be defined in software the date is automatically adjusted for leap years, assuming ev ery year divisible by 4 is a leap year. therefore, the reference value must be a leap year, e.g. 2000. the rtc will increment until it reaches the top value of 23:59:59 december 31 of year 63, and then wrap to 00:00:00 january 1 of year 0. this will set the overflow interrupt flag in the interrupt flag status and clear registers (intflag.ovf). the clock value is continuously compared with the 32-bit al arm register (alarm0). when an alarm match occurs, the alarm 0 interrupt flag in the interrupt flag status and clear registers (intflag.alarmn0) is set on the next 0-to-1 transition of clk_rtc_cnt. a valid alarm match depends on the setting of the alarm mask se lection bits in the alarm 0 mask register (mask0.sel). these bits determine which time/date fields of the clo ck and alarm values are valid for comparison and which are ignored.
208 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 if the clear on match bit in the control register (ctrl.ma tchclr) is one, the counter is cleared on the next counter cycle when an alarm match with alarm0 occurs. this allows the rtc to generate periodic interrupts or events with longer periods than are possible with the prescaler events (see ?periodic events? on page 208 ). note that when ctrl.matchclr is one, intflag.ala rm0 and intflag.ovf will both be set simultaneously on an alarm match with alarm0. 19.6.4 additional features 19.6.4.1 periodic events the rtc prescaler can generate events at periodic intervals, allowing flexible system tick creation. any of the upper eight bits of the prescaler (bits 2 to 9) can be the source of an event. when one of the periodic event output bits in the event control register (evctrl.pereom) is one, an event is generated on the 0-to1 transition of the related bit in the prescaler, resulting in a periodic event frequency of: f gclk_rtc is the frequency of the internal prescaler clock, gclk_rtc, and n is the position of the evctrl.perneo bit. for example, per0 will generate an event every 8 gclk_rtc cycles, per1 every 16 cycles, etc. this is shown in figure 19-4 . periodic events are independent of the prescaler setting used by the rtc counter, except if ctrl.prescaler is zero. then, no periodic events will be generated. figure 19-4. example periodic events 19.6.4.2 frequency correction the rtc frequency correction module employs periodic counter corrections to comp ensate for a too-slow or too-fast oscillator. frequency correction requires t hat ctrl.prescaler is greater than 1. the digital correction circuit adds or subtracts cycles fr om the rtc prescaler to adjust the frequency in approximately 1ppm steps. digital correction is achieved by adding or skipping a single count in the prescaler once every 1024 gclk_rtc cycles. the value bit group in the frequency co rrection register (freqcorr.value) determines the number of times the adjustment is applied over 976 of t hese periods. the resulting correction is as follows: this results in a resolution of 1.0006ppm. the sign bit in the frequency correction register (freqcorr.sign) determines the direction of the correction. a positive value will speed up the frequency, and a negative value will slow down the frequency. digital correction also affects the generation of the periodic events from the prescaler. when the correction is applied at the end of the correction cycle period, the interval between the previous periodic event and the next occurrence may also be shortened or lengthened depending on the correction value. 3 _ 2 + = n rtc gclk periodic f f gclk_rtc per0 per1 per2 per3 per4 correction in ppm freqcorr.value 1024 976 ? ----------------------------------------------------- 10 6 ppm ? =
209 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.6.5 dma operation not applicable. 19.6.6 interrupts the rtc has the following interrupt sources: z overflow z compare m z alarm m z synchronization ready each interrupt source has an interrupt flag associated with i t. the interrupt flag in the interrupt flag status and clear register (intflag) is set when the interrupt condition occu rs. each interrupt can be individually enabled by writing a one to the corresponding bit in the interrupt enable set regi ster (intenset), and disabled by writing a one to the corresponding bit in the interrupt enable clear register (int enclr). an interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the rtc is reset. see intflag for details on how to clear interrupt flags. the rtc has one common interrupt request line for all the interrupt s ources. the user must read intflag to determine which interrupt condition is present. note that interrupts must be globally enabled for interrupt requests to be generated. refer to ?nested vector interrupt controller? on page 28 for details. 19.6.7 events the rtc can generate the following output events, which are generated in the same way as the corresponding interrupts: z overflow (ovf) z period n (pern) z compare n (cmpn) z alarm n (alarmn) output events must be enabled to be generated. writing a one to an event output bit in the event control register (evctrl.xxeo) enables the corresponding output event. writing a zero to this bit disables the corresponding output event. refer to ?evsys ? event system? on page 314 for details. 19.6.8 sleep mode operation the rtc will continue to operate in any sleep mode where the source clock is active. the rtc interrupts can be used to wake up the device from a sleep mode, or the rtc events can trigger other operations in the system without exiting the sleep mode. an interrupt request will be generated after the wake-up if the interrupt controller is configured accordingly. otherwise the cpu will wake up directly, without triggering an interrupt. in this case, the cpu will continue executing from the instruction following the entry into sleep. the periodic events can also wake up the cpu through the interrupt function of the event system. in this case, the event must be enabled and connected to an event channel with its interrupt enabled. see ?evsys ? event system? on page 314 for more information. 19.6.9 synchronization due to the asynchronicity between clk_rtc_apb and gc lk_rtc some registers must be synchronized when accessed. a register can require: z synchronization when written z synchronization when read
210 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z synchronization when written and read z no synchronization when executing an operation that requires synchronization, the synchronization busy bit in the status register(status.syncbusy) will be set immediately, and cleared when synchronization is complete. the synchronization ready interrupt can be used to signal when sync is complete. this can be accessed via the synchronization ready interrupt flag in the interrupt flag status and clear register (intflag.syncrdy). if an operation that requires synchronization is executed wh ile status.syncbusy is one, the bus will be stalled. all operations will complete successfully, but the cpu will be stalled and interrupts will be pending as long as the bus is stalled. the following bits need synchronization when written: z software reset bit in the control register (ctrl.swrst) z enable bit in the control register (ctrl.enable) the following registers need synchronization when written: z the counter value register (count) z the clock value register (clock) z the counter period register (per) z the compare n value registers (compn) z the alarm n value registers (alarmn) z the frequency correction register (freqcorr) z the alarm n mask register (maskn) write-synchronization is denoted by the write-sync hronization property in the register description. the following registers need synchronization when read: z the counter value register (count) z the clock value register (clock) read-synchronization is denoted by the read-synchronization property in the register description.
211 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.7 register summary the register mapping depends on the operating mode bits in the control register (ctrl.mode). the register summary is presented for each of the three modes. table 19-1. register summary - mode 0 registers offset name bit pos. 0x00 ctrl 7:0 matchclr clkrep mode[1:0] enable swrst 0x01 15:8 prescaler[3:0] 0x02 readreq 7:0 addr[5:0] 0x03 15:8 rreq rcont 0x04 evctrl 7:0 pereo7 pereo6 pereo5 pereo4 pereo3 pereo2 pereo1 pereo0 0x05 15:8 ovfeo cmpeo0 0x06 intenclr 7:0 ovf syncrdy cmp0 0x07 intenset 7:0 ovf syncrdy cmp0 0x08 intflag 7:0 ovf syncrdy cmp0 0x09 reserved 0x0a status 7:0 syncbusy 0x0b dbgctrl 7:0 dbgrun 0x0c freqcorr 7:0 sign value[6:0] 0x0d reserved 0x0e reserved 0x0f reserved 0x10 count 7:0 count[7:0] 0x11 15:8 count[15:8] 0x12 23:16 count[23:16] 0x13 31:24 count[31:24] 0x14 reserved 0x15 reserved 0x16 reserved 0x17 reserved 0x18 comp0 7:0 comp[7:0] 0x19 15:8 comp[15:8] 0x1a 23:16 comp[23:16] 0x1b 31:24 comp[31:24]
212 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 19-2. register summary - mode 1 registers offset name bit pos. 0x00 ctrl 7:0 matchclr clkrep mode[1:0] enable swrst 0x01 15:8 prescaler[3:0] 0x02 readreq 7:0 addr[5:0] 0x03 15:8 rreq rcont 0x04 evctrl 7:0 pereo7 pereo6 pereo5 pereo4 pereo3 pereo2 pereo1 pereo0 0x05 15:8 ovfeo cmpeo1 cmpeo0 0x06 intenclr 7:0 ovf syncrdy cmp1 cmp0 0x07 intenset 7:0 ovf syncrdy cmp1 cmp0 0x08 intflag 7:0 ovf syncrdy cmp1 cmp0 0x09 reserved 0x0a status 7:0 syncbusy 0x0b dbgctrl 7:0 dbgrun 0x0c freqcorr 7:0 sign value[6:0] 0x0d reserved 0x0e reserved 0x0f reserved 0x10 count 7:0 count[7:0] 0x11 15:8 count[15:8] 0x12 reserved 0x13 reserved 0x14 per 7:0 per[7:0] 0x15 15:8 per[15:8] 0x16 reserved 0x17 reserved 0x18 comp0 7:0 comp[7:0] 0x19 15:8 comp[15:8] 0x1a comp1 7:0 comp[7:0] 0x1b 15:8 comp[15:8]
213 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 19-3. register summary - mode 2 registers offset name bit pos. 0x00 ctrl 7:0 matchclr clkrep mode[1:0] enable swrst 0x01 15:8 prescaler[3:0] 0x02 readreq 7:0 addr[5:0] 0x03 15:8 rreq rcont 0x04 evctrl 7:0 pereo7 pereo6 pereo5 pereo4 pereo3 pereo2 pereo1 pereo0 0x05 15:8 ovfeo alarmeo0 0x06 intenclr 7:0 ovf syncrdy alarm0 0x07 intenset 7:0 ovf syncrdy alarm0 0x08 intflag 7:0 ovf syncrdy alarm0 0x09 reserved 0x0a status 7:0 syncbusy 0x0b dbgctrl 7:0 dbgrun 0x0c freqcorr 7:0 sign value[6:0] 0x0d reserved 0x0e reserved 0x0f reserved 0x10 clock 7:0 minute[1:0] second[5:0] 0x11 15:8 hour[3:0] minute[5:2] 0x12 23:16 month[1:0] day[4:0] hour[4] 0x13 31:24 year[5:0] month[3:2] 0x14 reserved 0x15 reserved 0x16 reserved 0x17 reserved 0 x18 alarm0 7:0 minute[1:0] second[5:0] 0x19 15:8 hour[3:0] minute[5:2] 0x1a 23:16 month[1:0] day[4:0] hour[4] 0x1b 31:24 year[5:0] month[3:2] 0x1c mask0 7:0 sel[2:0]
214 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each individual register description. please refer to ?register access protection? on page 205 for details. some registers require synchronization when read and/or wr itten. synchronization is denoted by the write-synchronized or the read-synchronized property in each indi vidual register description. please refer to ?synchronization? on page 209 for details. some registers are enable-protected, meaning they can only be written when the rtc is dis abled. enable-protection is denoted by the enable-protected property in each individual register description.
215 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.1 control 19.8.1.1 mode 0 name: ctrl offset: 0x00 reset: 0x0000 property: write-protected, enable-protected, write-synchronized z bits 15:12 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 11:8 ? prescaler[3:0]: prescaler these bits define the prescaling factor for the rtc clock source (gclk_rtc) to generate the counter clock (clk_rtc_cnt). these bits are not synchronized. bit151413121110 9 8 prescaler[3:0] access r r r r r/w r/w r/w r/w reset00000000 bit76543210 matchclr mode[1:0] enable swrst access r/w r/w r r r/w r/w r/w r/w reset00000000 table 19-4. prescaler prescaler[3:0] prescaler description 0x0 div1 clk_rtc_cnt = gclk_rtc/1 0x1 div2 clk_rtc_cnt = gclk_rtc/2 0x2 div4 clk_rtc_cnt = gclk_rtc/4 0x3 div8 clk_rtc_cnt = gclk_rtc/8 0x4 div16 clk_rtc_cnt = gclk_rtc/16 0x5 div32 clk_rtc_cnt = gclk_rtc/32 0x6 div64 clk_rtc_cnt = gclk_rtc/64 0x7 div128 clk_rtc_cnt = gclk_rtc/128 0x8 div256 clk_rtc_cnt = gclk_rtc/256 0x9 div512 clk_rtc_cnt = gclk_rtc/512 0xa div1024 clk_rtc_cnt = gclk_rtc/1024 0xb-0xf - reserved
216 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bit 7 ? matchclr: clear on match this bit is valid only in mode 0 and mode 2. this bi t can be written only when the peripheral is disabled. 0: the counter is not cleared on a compare/alarm 0 match. 1: the counter is cleared on a compare/alarm 0 match. this bit is not synchronized. z bits 6:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 3:2 ? mode[1:0]: operating mode these bits define the operating mode of the rtc. these bits are not synchronized. z bit 1 ? enable: enable 0: the peripheral is disabled or being disabled. 1: the peripheral is enabled or being enabled. due to synchronization, there is delay from writing ctrl.enable until the peripheral is enabled/disabled. the value written to ctrl.enable will read back immediately, and the synchronization busy bit in the status register (status.syncbusy) will be set. status.syncbusy will be cleared when the operation is complete. this bit is not enable-protected. z bit 0 ? swrst: software reset 0: there is no reset operation ongoing. 1: the reset operation is ongoing. writing a zero to this bit has no effect. writing a one to this bit resets all registers in the rtc, except dbgctrl, to their initial state, and the rtc will be disabled. writing a one to ctrl.swrst will always take precedence, meaning that all other writes in the same write-oper- ation will be discarded. due to synchronization, there is a delay from writing ctrl.swrst until the reset is complete. ctrl.swrst and status.syncbusy will both be cleared when the reset is complete. this bit is not enable-protected. table 19-5. peripheral operating mode mode[1:0] operating mode description 0x0 count32 mode 0: 32-bit counter 0x1 count16 mode 1: 16-bit counter 0x2 clock mode 2: clock/calendar 0x3 - reserved
217 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.1.2 mode 1 name: ctrl offset: 0x00 reset: 0x0000 property: write-protected, enable-protected, write-synchronized z bits 15:12 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 11:8 ? prescaler[3:0]: prescaler these bits define the prescaling factor for the rtc clock source (gclk_rtc) to generate the counter clock (clk_rtc_cnt). these bits are not synchronized. bit151413121110 9 8 prescaler[3:0] access r r r r r/w r/w r/w r/w reset00000000 bit76543210 mode[1:0] enable swrst access r/w r/w r r r/w r/w r/w r/w reset00000000 table 19-6. prescaler prescaler[3:0] prescaler description 0x0 div1 clk_rtc_cnt = gclk_rtc/1 0x1 div2 clk_rtc_cnt = gclk_rtc/2 0x2 div4 clk_rtc_cnt = gclk_rtc/4 0x3 div8 clk_rtc_cnt = gclk_rtc/8 0x4 div16 clk_rtc_cnt = gclk_rtc/16 0x5 div32 clk_rtc_cnt = gclk_rtc/32 0x6 div64 clk_rtc_cnt = gclk_rtc/64 0x7 div128 clk_rtc_cnt = gclk_rtc/128 0x8 div256 clk_rtc_cnt = gclk_rtc/256 0x9 div512 clk_rtc_cnt = gclk_rtc/512 0xa div1024 clk_rtc_cnt = gclk_rtc/1024 0xb-0xf - reserved
218 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bits 7:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 3:2 ? mode[1:0]: operating mode these bits define the operating mode of the rtc. these bits are not synchronized. z bit 1 ? enable: enable 0: the peripheral is disabled or being disabled. 1: the peripheral is enabled or being enabled. due to synchronization, there is delay from writing ctrl.enable until the peripheral is enabled/disabled. the value written to ctrl.enable will read back immediately, and the synchronization busy bit in the status register (status.syncbusy) will be set. status.syncbusy will be cleared when the operation is complete. this bit is not enable-protected. z bit 0 ? swrst: software reset 0: there is no reset operation ongoing. 1: the reset operation is ongoing. writing a zero to this bit has no effect. writing a one to this bit resets all registers in the rtc, except dbgctrl, to their initial state, and the rtc will be disabled. writing a one to ctrl.swrst will always take precedence, meaning that all other writes in the same write-oper- ation will be discarded. due to synchronization, there is a delay from writing ctrl.swrst until the reset is complete. ctrl.swrst and status.syncbusy will both be cleared when the reset is complete. this bit is not enable-protected. table 19-7. peripheral operating mode mode[1:0] operating mode description 0x0 count32 mode 0: 32-bit counter 0x1 count16 mode 1: 16-bit counter 0x2 clock mode 2: clock/calendar 0x3 - reserved
219 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.1.3 mode 2 name: ctrl offset: 0x00 reset: 0x0000 property: write-protected, enable-protected, write-synchronized z bits 15:12 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 11:8 ? prescaler[3:0]: prescaler these bits define the prescaling factor for the rtc clock source (gclk_rtc) to generate the counter clock (clk_rtc_cnt). these bits are not synchronized. bit151413121110 9 8 prescaler[3:0] access r r r r r/w r/w r/w r/w reset00000000 bit76543210 matchclr clkrep mode[1:0] enable swrst access r/w r/w r r r/w r/w r/w r/w reset00000000 table 19-8. prescaler prescaler[3:0] prescaler description 0x0 div1 clk_rtc_cnt = gclk_rtc/1 0x1 div2 clk_rtc_cnt = gclk_rtc/2 0x2 div4 clk_rtc_cnt = gclk_rtc/4 0x3 div8 clk_rtc_cnt = gclk_rtc/8 0x4 div16 clk_rtc_cnt = gclk_rtc/16 0x5 div32 clk_rtc_cnt = gclk_rtc/32 0x6 div64 clk_rtc_cnt = gclk_rtc/64 0x7 div128 clk_rtc_cnt = gclk_rtc/128 0x8 div256 clk_rtc_cnt = gclk_rtc/256 0x9 div512 clk_rtc_cnt = gclk_rtc/512 0xa div1024 clk_rtc_cnt = gclk_rtc/1024 0xb-0xf - reserved
220 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bit 7 ? matchclr: clear on match this bit is valid only in mode 0 and mode 2. this bi t can be written only when the peripheral is disabled. 0: the counter is not cleared on a compare/alarm 0 match. 1: the counter is cleared on a compare/alarm 0 match. this bit is not synchronized. z bit 6 ? clkrep: clock representation this bit is valid only in mode 2 and determines how the hours are represented in the clock value (clock) regis- ter. this bit can be written only when the peripheral is disabled. 0: 24 hour 1: 12 hour (am/pm) this bit is not synchronized. z bits 5:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 3:2 ? mode[1:0]: operating mode these bits define the operating mode of the rtc. these bits are not synchronized. z bit 1 ? enable: enable 0: the peripheral is disabled or being disabled. 1: the peripheral is enabled or being enabled. due to synchronization, there is delay from writing ctrl.enable until the peripheral is enabled/disabled. the value written to ctrl.enable will read back immediately, and the synchronization busy bit in the status register (status.syncbusy) will be set. status.syncbusy will be cleared when the operation is complete. this bit is not enable-protected. z bit 0 ? swrst: software reset 0: there is no reset operation ongoing. 1: the reset operation is ongoing. writing a zero to this bit has no effect. writing a one to this bit resets all registers in the rtc, except dbgctrl, to their initial state, and the rtc will be disabled. writing a one to ctrl.swrst will always take precedence, meaning that all other writes in the same write-oper- ation will be discarded. due to synchronization, there is a delay from writing ctrl.swrst until the reset is complete. ctrl.swrst and status.syncbusy will both be cleared when the reset is complete. this bit is not enable-protected. table 19-9. peripheral operating mode mode[1:0] operating mode description 0x0 count32 mode 0: 32-bit counter 0x1 count16 mode 1: 16-bit counter 0x2 clock mode 2: clock/calendar 0x3 - reserved
221 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.2 read request name: readreq offset: 0x02 reset: 0x0010 property: ? - z bit 15 ? rreq: read request writing a zero to this bit has no effect. writing a one to this bit requests synchronization of the register pointed to by the address bit group (read- req.addr) and sets the synchronization busy bit in the status register (status.syncbusy). z bit 14 ? rcont: read continuously writing a zero to this bit disables continuous synchronization. writing a one to this bit enables continuous synchronization of the register pointed to by readreq.addr. the register value will be synchronized aut omatically every time the register is updated. readreq.rcont prevents readreq.rreq from clearing automatically. this bit is cleared when the register pointed to by readreq.addr is written. z bits 13:6 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 5:0 ? addr: address these bits select the offset of the register that needs read synchronization. in the rtc only the count and clock registers, which share the same address, are available for read synchronization. therefore, the addr bit group is a read-only constant of 0x10. bit151413121110 9 8 rreq rcont accesswr/wrrrrrr reset00000000 bit76543210 addr[5:0] accessrrrrrrrr reset00010000
222 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.3 event control 19.8.3.1 mode 0 name: evctrl offset: 0x04 reset: 0x0000 property: write-protected, enable-protected z bit 15 ? ovfeo: overflow event output enable 0: overflow event is disabled and will not be generated. 1: overflow event is enabled and will be generated for every overflow. z bits 14:9 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 8 ? cmpeo0: compare 0 event output enable 0: compare 0 event is disabled and will not be generated. 1: compare 0 event is enabled and will be generated for every compare match. z bits 7:0 ? pereox: periodic interval x event output enable 0: periodic interval m event is disabled and will not be generated. 1: periodic interval m event is enabled and will be generated. bit151413121110 9 8 ovfeo cmpeo0 accessr/wrrrrrrr/w reset00000000 bit76543210 pereo7 pereo6 pereo5 pereo4 pereo3 pereo2 pereo1 pereo0 access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
223 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.3.2 mode 1 name: evctrl offset: 0x04 reset: 0x0000 property: write-protected, enable-protected z bit 15 ? ovfeo: overflow event output enable 0: overflow event is disabled and will not be generated. 1: overflow event is enabled and will be generated for every overflow. z bits 14:10 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 9 ? cmpeo1: compare event output enable 1 0: compare 1 event is disabled and will not be generated. 1: compare 1 event is enabled and will be generated for every compare match. z bit 8 ? cmpeo0: compare event output enable 0 0: compare 0 event is disabled and will not be generated. 1: compare 0 event is enabled and will be generated for every compare match. z bits 7:0 ? pereox: periodic interval x event output enable 0: periodic interval m event is disabled and will not be generated. 1: periodic interval m event is enabled and will be generated. bit151413121110 9 8 ovfeo cmpeo1 cmpeo0 accessr/wrrrrrr/wr/w reset00000000 bit76543210 pereo7 pereo6 pereo5 pereo4 pereo3 pereo2 pereo1 pereo0 access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
224 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.3.3 mode 2 name: evctrl offset: 0x04 reset: 0x0000 property: write-protected, enabled-protected z bit 15 ? ovfeo: overflow event output enable 0: overflow event is disabled and will not be generated. 1: overflow event is enabled and will be generated for every overflow. z bits 14:9 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 8 ? alarmeo0: alarm 0 event output enable 0: alarm 0 event is disabled and will not be generated. 1: alarm 0 event is enabled and will be generated for every alarm. z bits 7:0 ? pereox: periodic interval x event output enable 0: periodic interval n event is disabled and will not be generated. 1: periodic interval n event is enabled and will be generated. bit 151413121110 9 8 ovfeo alarmeo0 accessr/wrrrrrrr/w reset00000000 bit76543210 pereo7 pereo6 pereo5 pereo4 pereo3 pereo2 pereo1 pereo0 access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
225 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.4 interrupt enable clear this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable set register (intenset). 19.8.4.1 mode 0 name: intenclr offset: 0x06 reset: 0x00 property: write-protected z bit 7 ? ovf: overflow interrupt enable 0: the overflow interrupt is disabled. 1: the overflow interrupt is enabled, and an interrupt r equest will be generated when the overflow interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the overflow interrupt enable bit and disable the corresponding interrupt. z bit 6 ? syncrdy: synchronization ready interrupt enable 0: the synchronization ready interrupt is disabled. 1: the synchronization ready interrupt is enabled, and an interrupt request will be generated when the synchroni- zation ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the synchronization ready interrupt enable bit and disable the corresponding interrupt. z bits 5:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? cmp0: compare 0 interrupt enable 0: the compare 0 interrupt is disabled. 1: the compare 0 interrupt is enabled, and an interrupt request will be generated when the compare 0 interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the compare 0 interrupt enable bit and disable the corresponding interrupt. bit76543210 ovf syncrdy cmp0 accessr/wr/wrrrrrr/w reset00000000
226 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.4.2 mode 1 name: intenclr offset: 0x06 reset: 0x00 property: write-protected z bit 7 ? ovf: overflow interrupt enable 0: the overflow interrupt is disabled. 1: the overflow interrupt is enabled, and an interrupt r equest will be generated when the overflow interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the overflow interrupt enable bit and disable the corresponding interrupt. z bit 6 ? syncrdy: synchronization ready interrupt enable 0: the synchronization ready interrupt is disabled. 1: the synchronization ready interrupt is enabled, and an interrupt request will be generated when the synchroni- zation ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the synchronization ready interrupt enable bit and disable the corresponding interrupt. z bits 5:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? cmp1: compare 1 interrupt enable 0: the compare 1 interrupt is disabled. 1: the compare 1 interrupt is enabled, and an interrupt request will be generated when the compare 1 interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the compare 1 interrupt enable bit and disable the corresponding interrupt. z bit 0 ? cmp0: compare 0 interrupt enable 0: the compare 0 interrupt is disabled. 1: the compare 0 interrupt is enabled, and an interrupt request will be generated when the compare 0 interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the compare 0 interrupt enable bit and disable the corresponding interrupt. bit76543210 ovf syncrdy cmp1 cmp0 access r/w r/w r r r r r/w r/w reset00000000
227 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.4.3 mode 2 name: intenclr offset: 0x06 reset: 0x00 property: write-protected z bit 7 ? ovf: overflow interrupt enable 0: the overflow interrupt is disabled. 1: the overflow interrupt is enabled, and an interrupt r equest will be generated when the overflow interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the overflow interrupt enable bit and disable the corresponding interrupt. z bit 6 ? syncrdy: synchronization ready interrupt enable 0: the synchronization ready interrupt is disabled. 1: the synchronization ready interrupt is enabled, and an interrupt request will be generated when the synchroni- zation ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the synchronization ready interrupt enable bit and disable the corresponding interrupt. z bits 5:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? alarm0: alarm 0 interrupt enable 0: the alarm 0 interrupt is disabled. 1: the alarm 0 interrupt is enabled, and an interrupt request will be generated when the alarm 0 interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit disables the alarm 0 interrupt. bit76543210 ovf syncrdy alarm0 accessr/wr/wrrrrrr/w reset00000000
228 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.5 interrupt enable set this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear (intenclr) register. 19.8.5.1 mode 0 name: intenset offset: 0x07 reset: 0x00 property: write-protected z bit 7 ? ovf: overflow interrupt enable 0: the overflow interrupt is disabled. 1: the overflow interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the overflow interrupt enable bit and enable the overflow interrupt. z bit 6 ? syncrdy: synchronization ready interrupt enable 0: the synchronization ready interrupt is disabled. 1: the synchronization ready interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the synchronization ready interrupt enable bit and enable the synchronization ready interrupt. z bits 5:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? cmp0: compare 0 interrupt enable 0: the compare 0 interrupt is disabled. 1: the compare 0 interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the compare 0 interrupt enable bit and enable the compare 0 interrupt. bit76543210 ovf syncrdy cmp0 accessr/wr/wrrrrrr reset00000000
229 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.5.2 mode 1 name: intenset offset: 0x07 reset: 0x00 property: write-protected z bit 7 ? ovf: overflow interrupt enable 0: the overflow interrupt is disabled. 1: the overflow interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the overflow interrupt bit and enable the overflow interrupt. z bit 6 ? syncrdy: synchronization ready interrupt enable 0: the synchronization ready interrupt is disabled. 1: the synchronization ready interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the synchronization ready interrupt enable bit and enable the synchronization ready interrupt. z bits 5:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? cmp1: compare 1 interrupt enable 0: the compare 1 interrupt is disabled. 1: the compare 1 interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the compare 1 interrupt enable bit and enable the compare 1 interrupt. z bit 0 ? cmp0: compare 0 interrupt enable 0: the compare 0 interrupt is disabled. 1: the compare 0 interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the compare 0 interrupt enable bit and enable the compare 0 interrupt. bit76543210 ovf syncrdy cmp1 cmp0 access r/w r/w r r r r r/w r/w reset00000000
230 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.5.3 mode 2 name: intenset offset: 0x07 reset: 0x00 property: write-protected z bit 7 ? ovf: overflow interrupt enable 0: the overflow interrupt is disabled. 1: the overflow interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the overflow interrupt enable bit and enable the overflow interrupt. z bit 6 ? syncrdy: synchronization ready interrupt enable 0: the synchronization ready interrupt is disabled. 1: the synchronization ready interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the synchronization ready interrupt bit and enable the synchronization ready interrupt. reading this bit returns the state of the synchronization ready interrupt enable. z bits 5:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? alarm0: alarm0 interrupt enable 0: the alarm 0 interrupt is disabled. 1: the alarm 0 interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the alarm 0 interrupt enable bit and enable the alarm 0 interrupt. bit76543210 ovf syncrdy alarm0 accessr/wr/wrrrrrr/w reset00000000
231 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.6 interrupt flag status and clear 19.8.6.1 mode 0 name: intflag offset: 0x08 reset: 0x00 property: - z bit 7 ? ovf: overflow this flag is cleared by writing a one to the flag. this flag is set on the next clk_rtc_cnt cycle after an overflow condition occurs, and an interrupt request will be generated ifintenclr/set.ovf is one. writing a zero to this bit has no effect. writing a one to this bit clears the overflow interrupt flag. z bit 6 ? syncrdy: synchronization ready this flag is cleared by writing a one to the flag. this flag is set on a 1-to-0 transition of the synchroniza tion busy bit in the status register (status.syncbusy), except when caused by enable or software reset, and an interrupt request will be generated if inten- clr/set.syncrdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the synchronization ready interrupt flag. z , and an interrupt request will be generated bits 5:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? cmp0: compare 0 this flag is cleared by writing a one to the flag. this flag is set on the next clk_rtc_cnt cycle after a match with the compare condition, and an interrupt request will be generated if intenclr/set.comp0 is one. writing a zero to this bit has no effect. writing a one to this bit clears the compare 0 interrupt flag. bit76543210 ovf syncrdy cmp0 access r/w r/w r r r r r r/w reset00000000
232 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.6.2 mode 1 name: intflag offset: 0x08 reset: 0x00 property: - z bit 7 ? ovf: overflow this flag is cleared by writing a one to the flag. this flag is set on the next clk_rtc_cnt cycle after an overflow condition occurs, and an interrupt request will be generated ifintenclr/set.ovf is one. writing a zero to this bit has no effect. writing a one to this bit clears the overflow interrupt flag. z bit 6 ? syncrdy: synchronization ready this flag is cleared by writing a one to the flag. this flag is set on a 1-to-0 transition of the synchroniza tion busy bit in the status register (status.syncbusy), except when caused by enable or software reset, and an interrupt request will be generated if inten- clr/set.syncrdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the synchronization ready interrupt flag. z , and an interrupt request will be generated bits 5:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? cmp1: compare 1 this flag is cleared by writing a one to the flag. this flag is set on the next clk_rtc_cnt cycle after a match with the compare condition, and an interrupt request will be generated if intenclr/set.comp1 is one. writing a zero to this bit has no effect. writing a one to this bit clears the compare 1 interrupt flag. z bit 0 ? cmp0: compare 0 this flag is cleared by writing a one to the flag. this flag is set on the next clk_rtc_cnt cycle after a match with the compare condition, and an interrupt request will be generated if intenclr/set.comp0 is one. writing a zero to this bit has no effect. writing a one to this bit clears the compare 0 interrupt flag. bit76543210 ovf syncrdy cmp1 cmp0 access r/w r/w r r r r r/w r/w reset00000000
233 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.6.3 mode 2 name: intflag offset: 0x08 reset: 0x00 property: ? z bit 7 ? ovf: overflow this flag is cleared by writing a one to the flag. this flag is set on the next clk_rtc_cnt cycle after an overflow condition occurs, and an interrupt request will be generated ifintenclr/set.ovf is one. writing a zero to this bit has no effect. writing a one to this bit clears the overflow interrupt flag. z bit 6 ? syncrdy: synchronization ready this flag is cleared by writing a one to the flag. this flag is set on a 1-to-0 transition of the synchroniza tion busy bit in the status register (status.syncbusy), except when caused by enable or software reset, and an interrupt request will be generated if inten- clr/set.syncrdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the synchronization ready interrupt flag. z , and an interrupt request will be generated bits 5:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? alarm0: alarm 0 this flag is cleared by writing a one to the flag. this flag is set on the next clk_rtc_cnt cycle after a match with alarm0 condition occurs, and an interrupt request will be generated if intenclr/set.alarm0 is also one. writing a zero to this bit has no effect. writing a one to this bit clears the alarm 0 interrupt flag. bit76543210 ovf syncrdy alarm0 accessr/wr/wrrrrrr/w reset00000000
234 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.7 status name: status offset: 0x0a reset: 0x00 property: ? z bit 7 ? syncbusy: synchronization busy this bit is cleared when the synchronization of registers between the clock domains is complete. this bit is set when the synchronization of registers between clock domains is started. z bits 6:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. bit76543210 syncbusy accessrrrrrrrr reset00000000
235 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.8 debug control name: dbgctrl offset: 0x0b reset: 0x00 property: ? z bits 7:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? dbgrun: run during debug this bit is not reset by a software reset. writing a zero to this bit causes the rtc to halt during debug mode. writing a one to this bit allows the rtc to continue normal operation during debug mode. bit76543210 dbgrun accessrrrrrrrr/w reset00000000
236 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.9 frequency correction name: freqcorr offset: 0x0c reset: 0x00 property: write-protected, write-synchronized z bit 7 ? sign: correction sign 0: the correction value is positive, i.e., frequency will be increased. 1: the correction value is negative, i.e., frequency will be decreased. z bits 6:0 ? value[6:0]: correction value these bits define the amount of correction applied to the rtc prescaler. 0: correction is disabled and the rtc frequency is unchanged. 1?127: the rtc frequency is adjusted according to the value. bit76543210 sign value[6:0] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000
237 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.10 counter value 19.8.10.1 mode 0 name: count offset: 0x10 reset: 0x00000000 property: write-protected, write-synchronized, read-synchronized z bits 31:0 ? count[31:0]: counter value these bits define the value of the 32-bit rtc counter. bit 3130292827262524 count[31:24] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 count[23:16] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 count[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 count[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
238 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.10.2 mode 1 name: count offset: 0x10 reset: 0x0000 property: write-protected, write-synchronized, read-synchronized z bits 15:0 ? count[15:0]: counter value these bits define the value of the 16-bit rtc counter. bit 151413121110 9 8 count[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 count[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
239 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.11 clock value 19.8.11.1 mode 2 name: clock offset: 0x10 reset: 0x00000000 property: write-protected, write-synchronized, read-synchronized z bits 31:26 ? year[5:0]: year the year offset with respect to the reference year (defined in software). the year is considered a leap year if year[1:0] is zero. z bits 25:22 ? month[3:0]: month 1 ? january 2 ? february ? 12 ? december z bits 21:17 ? day[4:0]: day day starts at 1 and ends at 28, 29, 30 or 31, depending on the month and year. z bits 16:12 ? hour[4:0]: hour when ctrl.clkrep is zero, the hour bit group is in 24- hour format, with values 0-23. when ctrl.clkrep is one, hour[3:0] has values 1-12 and hour[4] represents am (0) or pm (1). z bits 11:6 ? minute[5:0]: minute 0 ? 59. bit 3130292827262524 year[5:0] month[3:2] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 month[1:0] day[4:0] hour[4] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 hour[3:0] minute[5:2] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 minute[1:0] second[5:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
240 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bits 5:0 ? second[5:0]: second 0? 59.
241 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.12 counter period 19.8.12.1 mode 1 name: per offset: 0x14 reset: 0x0000 property: write-protected, write-synchronized z bits 15:0 ? per[15:0]: counter period these bits define the value of the 16-bit rtc period. bit 151413121110 9 8 per[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 76543210 per[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
242 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.13 compare n value 19.8.13.1 mode 0 name: compn offset: 0x18 + n*0x4 [n=0..3] reset: 0x00000000 property: write-protected, write-synchronized z bits 31:0 ? comp[31:0]: compare value the 32-bit value of compn is continuously compared with the 32-bit count value. when a match occurs, the compare n interrupt flag in the interrupt flag status and clear register (intflag.cmpn) is set on the next counter cycle, and the counter value is cleared if ctrl.matchclr is one. bit 3130292827262524 comp[31:24] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 comp[23:16] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 comp[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 comp[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
243 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.13.2 mode 1 name: compn offset: 0x18 + n*0x2 [n=0..5] reset: 0x0000 property: write-protected, write-synchronized z bits 15:0 ? comp[15:0]: compare value the 16-bit value of compn is continuously compared with the 16-bit count value. when a match occurs, the compare n interrupt flag in the interrupt flag status and clear register (intflag.cmpn) is set on the next counter cycle. bit 151413121110 9 8 comp[15:8] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000 bit76543210 comp[7:0] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000
244 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.14 alarm n value 19.8.14.1 mode 2 name: alarmn offset: 0x18 + n*0x8 [n=0..3] reset: 0x00000000 property: write-protected, write-synchronized the 32-bit value of alarmn is continuously compared with the 32-bit clock value, based on the masking set by maskn.sel. when a match occurs, the alarm n interrupt flag in the interrupt flag status and clear register (intflag.alarmn) is set on the next counter cycle, and the counter is cleared if ctrl.matchclr is one. z bits 31:26 ? year[5:0]: year the alarm year. years are onl y matched if maskn.sel is 6. z bits 25:22 ? month[3:0]: month the alarm month. months are matched only if maskn.sel is greater than 4. z bits 21:17 ? day[4:0]: day the alarm day. days are matched only if maskn.sel is greater than 3. z bits 16:12 ? hour[4:0]: hour the alarm hour. hours are matched only if maskn.sel is greater than 2. z bits 11:6 ? minute[5:0]: minute the alarm minute. minutes are matched only if maskn.sel is greater than 1. bit 3130292827262524 year[5:0] month[3:2] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 month[1:0] day[4:0] hour[4] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 hour[3:0] minute[5:2] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 minute[1:0] second[5:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
245 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bits 5:0 ? second[5:0]: second the alarm second. seconds are matched only if maskn.sel is greater than 0.
246 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 19.8.15 alarm n mask 19.8.15.1 mode 2 name: maskn offset: 0x1c + n*0x8 [n=0..3] reset: 0x00 property: write-protected, write-synchronized z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 2:0 ? sel[2:0]: alarm mask selection these bits define which bit groups of alarm n are valid. bit76543210 sel[2:0] access r r r r r r/w r/w r/w reset00000000 table 19-10. alarm mask selection sel[2:0] alarm mask selection description 0x0 off alarm disabled 0x1 ss match seconds only 0x2 mmss match seconds and minutes only 0x3 hhmmss match seconds, minutes and hours only 0x4 ddhhmmss match seconds, minutes, hours and days only 0x5 mmddhhmmss match seconds, minutes, hours, days and months only 0x6 yymmddhhmmss match seconds, minutes, hours, days, months and years 0x7 - reserved
247 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20. eic ? external interrupt controller 20.1 overview the external interrupt controller (eic) allows external pins to be configured as interrupt lines. each interrupt line can be individually masked and can generate an interrupt on rising, falling or both edges, or on high or low levels. each external pin has a configurable filter to remove spikes. each exter nal pin can also be configured to be asynchronous in order to wake up the device from sleep modes where all clocks have been disabled. external pins can also generate an event. a separate non-maskable interrupt (nmi) is also supported. it has properties similar to the other external interrupts, but is connected to the nmi request of the cpu, enabling it to interrupt any other interrupt mode. 20.2 features z 16 external pins, plus 1 non-maskable pin z dedicated interrupt line for each pin z individually maskable interrupt lines z interrupt on rising, falling or both edges z interrupt on high or low levels z asynchronous interrupts for sleep modes without clock z filtering of external pins z event generation z configurable wake-up for sleep modes 20.3 block diagram figure 20-1. eic block diagram fil ter ed g e / level detection i nterru pt w ake e vent filtenx extintx intre q_ extint [ x ] inwake _ extint [ x ] e vt _ extint [ x ] fil t e r edge/level de t ec t io n i nterrup t wa k e nmifilten nmi s en s e[2:0] nmi intre q_ nm i inwake_nmi sensex [ 2:0 ]
248 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.4 signal description please refer to ?i/o multiplexing and considerations? on page 15 for details on the pin mapping for this peripheral. one signal can be mapped on several pins. 20.5 product dependencies in order to use this eic, other parts of the system must be configured correctly, as described below. 20.5.1 i/o lines using the eic?s i/o lines requires the i/o pins to be configured. refer to ?port? on page 289 for details. 20.5.2 power management all interrupts are available in all sleep modes, but the eic can be configured to automatically mask some interrupts in order to prevent device wake-up. the eic will continue to operate in any sleep mode where the selected source clock is running. the eic?s interrupts can be used to wake up the device from sleep modes. events connect ed to the event system can trigger other operations in the system without exiting sleep modes. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. 20.5.3 clocks the eic bus clock (clk_eic_apb) can be enabled and disabled in the power manager, and the default state of clk_eic_apb can be found in the peripheral clock masking section in ?pm ? power manager? on page 105 . a generic clock (gclk_eic) is required to clock the per ipheral. this clock must be configured and enabled in the generic clock controller before using the peripheral. please refer to ?gclk ? generic clock controller? on page 83 for details. this generic clock is asynchronous to the user interface cl ock (clk_eic_apb). due to this asynchronicity, writes to certain registers will require synchronizati on between the clock domains. please refer to ?synchronization? on page 252 for further details. 20.5.4 interrupts there are two interrupt request lines, one for the external interrupts (extint) and one for non-maskable interrupt (nmi). the extint interrupt request line is connected to the interrupt controller. using the eic interrupt requires the interrupt controller to be configured first. please refer to ?nested vector interrupt controller? on page 28 for details. the nmi interrupt request line is also connected to the interrupt controller, but does not require the interrupt to be configured. 20.5.5 events the events are connected to the event system. using the events requires the event system to be configured first. please refer to ?evsys ? event system? on page 314 for details. signal name type description extint[15..0] digital input external interrupt pin nmi digital input non-maskable interrupt pin
249 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.5.6 debug operation when the cpu is halted in debug mode, the eic continues normal operation. if the eic is configured in a way that requires it to be periodically serviced by the cpu through inte rrupts or similar, improper operation or data loss may result during debugging. 20.5.7 register access protection all registers with write-access are optionally write-protected by the peripheral access controller (pac), except the following registers: z interrupt flag status and clear register (intflag) z non-maskable interrupt flag status and clear register (nmiflag) write-protection is denoted by the write-protected property in the register description. write-protection does not apply to accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details. 20.5.8 analog connections not applicable. 20.6 functional description 20.6.1 principle of operation the eic detects edge or level condition to generate interrupts to the cpu interrupt controller or events to the event system. each external interrupt pin (extint) can be filter ed using majority vote filtering, clocked by generic clock gclk_eic. 20.6.2 basic operation 20.6.2.1 initialization the eic must be initialized in the following order: 1. enable clk_eic_apb 2. if edge detection or filtering is required, gclk_eic must be enabled 3. write the eic configuration register s (nmictrl, evctrl, wakeup, configy) 4. enable the eic when nmi is used, gclk_eic must be enabled after eic configuration 20.6.2.2 enabling, disabling and resetting the eic is enabled by writing a one to the enable bit in the control register (ctrl.enable). the eic is disabled by writing a zero to ctrl.enable. the eic is reset by writing a one to the software reset bit in the control register (ctrl.swrst). all registers in the eic will be reset to their initial state, and the eic will be disabled. refer to ctrl register for details. 20.6.3 external pin processing each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or both edges) or level detection (high or low). the sense of external pins is c onfigured by writing the interrupt sense x bits in the config y register (configy.sensex). the corr esponding interrupt flag (intflag.extint[x]) in the interrupt flag status and clear register (intflag) is set when the interrupt conditi on is met (configy.sensex must be different from zero).
250 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 when the interrupt has been cleared in edge-sensitive mode, intflag.extint[x] will only be set if a new interrupt condition is met. in level-sensitive mode, when interrupt has been cleared, intflag.extint[x] will be set immediately if the extintx pin still matches the interrupt condition. each external pin can be filtered by a majority vote filtering, clocked by gclk_eic. filteri ng is enabled if bit filter enable x in the configuration y register (configy.filtenx) is writt en to one. the majority vote filter samples the external pin three times with gclk_eic and outputs the value when two or more samples are equal. when an external interrupt is configured for level detection, or if filtering is disabled, detection is made asynchronously, and gclk_eic is not required. if filtering or edge detection is enabled, the eic automatically requests the gclk_eic to operate (gclk_eic must be enabled in the gclk module, see ?gclk ? generic clock controller? on page 83 for details). if level detection is enabled, gclk_eic is not required, but interrupt and events can still be generated. figure 20-2. interrupt detections the detection delay depends on the detection mode. table 20-1. majority vote filter samples [0, 1, 2] filter output [0,0,0] 0 [0,0,1] 0 [0,1,0] 0 [0,1,1] 1 [1,0,0] 0 [1,0,1] 1 [1,1,0] 1 [1,1,1] 1 g clk _ ei c c lk_ei c _apb e xtint x i ntreq_ext i nt [ x ] (level detection / no filter) i ntre q_ extint [ x ] (level detection / filter ) i ntre q_ extint [ x ] ( edge detection / no f ilter ) i ntre q_ extint [ x ] (edge detection / filter ) n o interru p t n o interru p t c lear intflag.extint [ x ]
251 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.6.4 additional features the non-maskable interrupt pin can also generate an interrupt on edge or level detection, but it is configured with the dedicated nmi control register (nmictrl). to select the sense for nmi, write to the nmisense bit group in the nmi control register (nmictrl.nmisense). nmi filtering is enabled by writing a one to the nmi filter enable bit (nmictrl.nmifilten). nmi detection is enabled only by the nmictrl.nmisense value, and the eic is not required to be enabled. after reset, nmi is configured to no detection mode. ----- when an nmi is detected, the non-maskable interrupt flag in the nmi flag status and clear register is set (nmiflag.nmi). nmi interrupt generation is always enabled, and nmiflag.nmi generates an interrupt request when set. 20.6.5 interrupts the eic has the following interrupt sources: z external interrupt pins (extintx). see ?basic operation? on page 249 z non-maskable interrupt pin (nmi). see ?additional features? on page 251 each interrupt source has an interrupt flag associated with i t. the interrupt flag in the interrupt flag status and clear register (intflag) is set when an interrupt condition occurs (nmiflag for nmi). each interrupt, except nmi, can be individually enabled by writing a one to the corresponding bit in the interrupt enable set register (intenset), and disabled by writing a one to the corresponding bit in the interr upt enable clear register (intenclr). an interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt request remains active until the interrupt flag is cleared, the inte rrupt is disabled or the eic is reset. see the intflag register for details on how to clear interrupt flags. the eic has one common interr upt request line for all the interrupt sources (except the nmi interrupt request line). refer to ?processor and architecture? on page 27 for details. the user must read the intflag (or nmiflag) register to dete rmine which interrupt condition is present. note that interrupts must be globally enabled for interrupt requests to be generated. refer to ?processor and architecture? on page 27 for details. 20.6.6 events the eic can generate the following output events: z external event from pin (extintx). writing a one to an event output control register (evctr lextinteo) enables the corresponding output event. writing a zero to this bit disables the corresponding output event. refer to ?evsys ? event system? on page 314 for details on configuring the event system. when the condition on pin extintx matches the configurati on in the configy register, the corresponding event is generated, if enabled. table 20-2. interrupt latency detection mode latency (worst case) level without filter 3 clk_eic_apb periods level with filter 4 gclk_eic periods + 3 clk_eic_apb periods edge without filter 4 gclk_eic periods + 3 clk_eic_apb periods edge with filter 6 gclk_eic periods + 3 clk_eic_apb periods
252 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.6.7 sleep mode operation in sleep modes, an extintx pin can wake up the device if the corresponding condition matches the configuration in configy register. writing a one to a wake-up enable bi t (wakeup.wakeupen[x]) enabl es the wake-up from pin extintx. writing a zero to a wake-up enable bit (wakeu p.wakeupen[x]) disables the wake-up from pin extintx. figure 20-3. wake-up operation example (high- level detection, no filter, wakeupen[x]=1) 20.6.8 synchronization due to the asynchronicity between clk_eic_apb and gclk_eic, some registers must be synchronized when accessed. a register can require: z synchronization when written z synchronization when read z synchronization when written and read z no synchronization when executing an operation that requires synchronization, the synchronization busy bit in the status register (status.syncbusy) will be set immediately, and cleared when synchronization is complete. the synchronization ready interrupt can be used to signal when sync is comple te. this can be accessed via the synchronization ready interrupt flag in the interrupt flag stat us and clear register (intflag.syncrdy). if an operation that requires synchronization is executed wh ile status.syncbusy is one, the bus will be stalled. all operations will complete successfully, but the cpu will be stalled, and interrupts will be pending as long as the bus is stalled. the following bits need synchronization when written: z software reset bit in the control register (ctrl.swrst) z enable bit in the control register (ctrl.enable) no register needs synchronization when written. no register needs synchronization when read. clk _ eic _ apb extintx intwake_extint[x] intre q_ extint [ x ] c lear intflag.extint [ x ] r eturn to slee p mode
253 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.7 register summary table 20-3. register summary offset name bit pos. 0x00 ctrl 7:0 enable swrst 0x01 status 7:0 syncbusy 0x02 nmictrl 7:0 nmifilten nmisense[2:0] 0x03 nmiflag 7:0 nmi 0x04 evctrl 7:0 extinteo[7:0] 0x05 15:8 extinteo[15:8] 0x06 23:16 0x07 31:24 0x08 intenclr 7:0 extint[7:0] 0x09 15:8 extint[15:8] 0x0a 23:16 0x0b 31:24 0x0c intenset 7:0 extint[7:0] 0x0d 15:8 extint[15:8] 0x0e 23:16 0x0f 31:24 0x10 intflag 7:0 extint[7:0] 0x11 15:8 extint[15:8] 0x12 23:16 0x13 31:24 0x14 wakeup 7:0 wakeupen[7:0] 0x15 15:8 wakeupen[15:8] 0x16 23:16 0x17 31:24 0x18 config0 7:0 filten1 sense1[2:0] filten0 sense0[2:0] 0x19 15:8 filten3 sense3[2:0] filten2 sense2[2:0] 0x1a 23:16 filten5 sense5[2:0] filten4 sense4[2:0] 0x1b 31:24 filten7 sense7[2:0] filten6 sense6[2:0] 0x1c config1 7:0 filten9 sense9[2:0] filten8 sense8[2:0] 0x1d 15:8 filten11 sense11[2:0] filten10 sense10[2:0] 0x1e 23:16 filten13 sense13[2:0] filten12 sense12[2:0] 0x1f 31:24 filten15 sense15[2:0] filten14 sense14[2:0]
254 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each indivi dual register description. please refer to ?register access protection? on page 249 for details. some registers require synchronization when read and/or written. synchronization is denoted by the synchronized property in each individual register description. please refer to ?synchronization? on page 252 for details. some registers are enable-protected, meaning they can be wr itten only when the eic is disabled. enable-protection is denoted by the enabled-protected property in each individual register description.
255 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.8.1 control name: ctrl offset: 0x00 reset: 0x00 property: write-protected,write-synchronized z bits 7:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? enable: enable 0: the eic is disabled. 1: the eic is enabled. due to synchronization, there is delay from writing ctrl.enable until the peripheral is enabled/disabled. the value written to ctrl.enable will read back immediately, and the synchronization busy bit in the status register (status.syncbusy) will be set. status.syncbusy will be cleared when the operation is complete. z bit 0 ? swrst: software reset 0: there is no ongoing reset operation. 1: the reset operation is ongoing. writing a zero to this bit has no effect. writing a one to this bit resets all registers in the eic to their initial state, and the eic will be disabled. writing a one to ctrl.swrst will always take precedence, meaning that all other writes in the same write opera- tion will be discarded. due to synchronization, there is a delay from writing ctrl.swrst until the reset is complete. ctrl.swrst and status.syncbusy will both be cleared when the reset is complete. bit 76543210 enable swrst accessrrrrrrr/wr/w reset00000000
256 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.8.2 status name: status offset: 0x01 reset: 0x00 property: - z bit 7 ? syncbusy: synchronization busy this bit is cleared when the synchronization of registers between the clock domains is complete. this bit is set when the synchronization of registers between clock domains is started. z bits 6:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. bit 7 6543210 syncbusy accessr rrrrrrr reset0 0000000
257 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.8.3 non-maskable interrupt control name: nmictrl offset: 0x02 reset: 0x00 property: write-protected z bits 7:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 3 ? nmifilten: non-maskab le interrupt filter enable 0: nmi filter is disabled. 1: nmi filter is enabled. z bits 2:0 ? nmisense: non -maskable interrupt sense these bits define on which edge or level the nmi triggers. bit 76543210 nmifilten nmisense[2:0] accessrrrrr/wr/wr/wr/w reset00000000 table 20-4. nmi sense configuration nmisense name description 0x0 none no detection 0x1 rise rising-edge detection 0x2 fall falling-edge detection 0x3 both both-edges detection 0x4 high high-level detection 0x5 low low-level detection 0x6-0x7 - reserved
258 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.8.4 non-maskable interrupt flag status and clear name: nmiflag offset: 0x03 reset: 0x00 property: - z bits 7:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? nmi: non-maskable interrupt this flag is cleared by writing a one to it. this flag is set when the nmi pin matches the nmi sense configuration, and will generate an interrupt request. writing a zero to this bit has no effect. writing a one to this bit clears the non-maskable interrupt flag. bit 76543210 nmi accessrrrrrrrr/w reset 00000000
259 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.8.5 event control name: evctrl offset: 0x04 reset: 0x00000000 property: write-protected z bits 31:16 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 15:0 ? extinteo: external interrupt x event output enable these bits indicate whether the event associated withthe extintx pin is enabled or not togenerated for every detection. 0: event from pin extintx is disabled. 1: event from pin extintx is enabled. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 extinteo[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 76543210 extinteo[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
260 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.8.6 interrupt enable clear this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable set register (intenset). name: intenclr offset: 0x08 reset: 0x00000000 property: write-protected z bits 31:16 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 15:0 ? extint: external interrupt x enable 0: the external interrupt x is disabled. 1: the external interrupt x is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the external interr upt x enable bit, which enables the external interrupt. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 extint[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 76543210 extint[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
261 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.8.7 interrupt enable set this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear (intenclr) register. name: intenset offset: 0x0c reset: 0x00000000 property: write-protected z bits 31:16 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 15:0 ? extint: external interrupt x enable 0: the external interrupt x is disabled. 1: the external interrupt x is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the external interr upt x enable bit, which enables the external interrupt. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 extint[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 76543210 extint[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
262 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.8.8 interrupt flag status and clear name: intflag offset: 0x10 reset: 0x00000000 property: - z bits 31:16 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 15:0 ? extint: external interrupt x this flag is cleared by writing a one to it. this flag is set when extintx pin matches the external interrupt sense configuration and will generate an interrupt request if intenclr/set.extint[x] is one. writing a zero to this bit has no effect. writing a one to this bit clears the external interrupt x flag. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 extint[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 76543210 extint[7:0] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000
263 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.8.9 wake-up enable name: wakeup offset: 0x14 reset: 0x00000000 property: write-protected z bits 31:16 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 15:0 ? wakeupen: external interrupt x wake-up enable this bit enables or disables wake-up from sleep modes when the extintx pin matches the external interrupt sense configuration. 0: wake-up from the extintx pin is disabled. 1: wake-up from the extintx pin is enabled. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 wakeupen[15:8] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000 bit 76543210 wakeupen[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
264 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 20.8.10 configuration n name: confign offset: 0x18+n*0x4 [n=0..1] reset: 0x00000000 property: write-protected z bits 31, 27, 23, 19, 15, 11, 7, 3 ? filtenx [x=7..0]: filter x enable 0: filter is disabled for extint[n*8+x] input. 1: filter is enabled for extint[n*8+x] input. z bits 30:28, 26:24, 22:20, 18:16, 14:12, 10:8, 6:4, 2:0 ? sensex[2:0] [x=7..0]: input sense x configuration these bits define on which edge or level the interrupt or event for extint[n*8+x] will be generated. bit 3130292827262524 filten7 sense7[2:0] filten6 sense6[2:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 filten5 sense5[2:0] filten4 sense4[2:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 filten3 sense3[2:0] filten2 sense2[2:0] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000 bit 76543210 filten1 sense1[2:0] filten0 sense0[2:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
265 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 20-5. sense configuration sense name description 0x0 none no detection 0x1 rise rising-edge detection 0x2 fall falling-edge detection 0x3 both both-edges detection 0x4 high high-level detection 0x5 low low-level detection 0x6-0x7 - reserved
266 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 21. nvmctrl ? non-volat ile memory controller 21.1 overview non-volatile memory (nvm) is a repr ogrammable flash memory that retains program and data storage even with power off. the nvm controller (nvmctrl) connects to the ahb and apb bus interfaces for system access to the nvm block. the ahb interface is used for reads and writes to the nvm block, while the apb interface is used for commands and configuration. 21.2 features z 32-bit ahb interface for reads and writes z all nvm sections are memory mapped to the ahb, including calibration and system configuration z 32-bit apb interface for commands and control z programmable wait states for read optimization z 16 regions can be individually protected or unprotected z additional protection for boot loader z supports device protection through a security bit z interface to power manager for power-down of flash blocks in sleep modes z can optionally wake up on exit from sleep or on first access z direct-mapped cache 21.3 block diagram figure 21-1. block diagram 21.4 signal description not applicable command and control nvm interface cache nvm block nvmctrl ahb apb
267 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 21.5 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 21.5.1 power management the nvmctrl will continue to operate in any sleep mode where the selected source clock is running. the nvmctrl?s interrupts can be used to wake up the device from sleep modes. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. the power manager will automatically put the nvm block into a low-power state when entering sleep mode. this is based on the control b register (ctrlb) sleepprm bit setting. read the ctrlb register description for more details. 21.5.2 clocks two synchronous clocks are used by the the nvmctrl. one is provided by the ah b bus (clk_nvmctrl_ahb) and the other is provided by the apb bus (clk_nvmctrl_a pb). for higher system frequencies, a programmable number of wait states can be used to optimize performance. when changing the ahb bus frequency, the user must ensure that the nvm controller is configured with the proper number of wait states. - 21.5.3 interrupts the nvm controller interrupt request line is connected to t he interrupt controller. using the nvmctrl interrupt requires the interrupt controller to be programmed first. 21.5.4 debug operation when an external debugger forces the cpu into debug mode, the peripheral continues normal operation. access to the nvm block can be protected by the security bit. in this case, the nvm block will not be accessible. see ?security bit? on page 273 for details. 21.5.5 register access protection all registers with write-access are optionally write-protected by the peripheral access controller (pac), except the following registers: z interrupt flag status and clear register (intflag) z status register (status) write-protection is denoted by the write-protected property in the register description. write-protection does not apply for accesses through an external debugger. when the cpu is halted in debug mode, all write-protection is automatically disabled. refer to ?pac ? peripheral access controller? on page 31 for details. 21.5.6 analog connections not applicable. 21.6 functional description 21.6.1 principle of operation the nvm controller is a slave on the ahb and apb buses. it responds to commands, read requests and write requests, based on user configuration. 21.6.1.1 initialization after power up, the nvm controller goes through a power-up sequence. during this time, access to the nvm controller from the ahb bus is halted. upon power-up completion, th e nvm controller is operati onal without any need for user configuration.
268 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 21.6.2 memory organization refer to ?product mapping? on page 23 for memory sizes and addresses for each device. the nvm is organized into rows, where each row contains four pages, as shown in figure 21-2 . the nvm has a row- erase granularity, while the write granularity is by page. in other words, a single row erase will erase all four pages in the row, while four write operations are used to write the complete row. figure 21-2. row organization z r rows z p pages z wr words per row z hw half words (16-bit) in each page and in the page buffer z pw words in total z aw words reserved for auxiliary space the nvm block contains an auxiliary space that is memory mapped, as shown in table 21-1 . the auxiliary space contains factory calibration and system c onfiguration information. this space can be read from the ahb bus in the same way as the main nvm main address space. in addition, a boot section can be allocated at the beginning of the main array, and an eeprom section can be allocated at the end of the nvm main address space. table 21-1. memory organization memory section start byte address size main address space 0 pw words = 4pw bytes calibration and auxiliary space 0x0080_0000 aw words = 8 bytes user row 0x0080_4000 1 row page (n * 4) + 0 row n page (n * 4) + 1 page (n * 4) + 2 page (n * 4) + 3
269 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 21-3. memory organization the lower rows in the nvm main address space can be allocated as a boot section by using the bootprot fuses, and the upper rows can be allocated to eeprom, as shown in figure 21-4 . the boot sections are protected by the lock bit(s) corresponding to this address space and by the bootprot[2:0] fuse. the eeprom rows can be written, regardless of the region lock status. the number of rows protected by bootprot and the number of rows allocated to the eeprom are given in table 21-4 and table , respectively. figure 21-4. eeprom and boot allocation 21.6.3 region lock bits the nvm block is grouped into 16 equally sized regions. t he region size is dependent on the flash memory size, and is given in the table below. each region has a dedicated lock bit preventing writing and erasing pages in the region. after production, all regions will be unlocked. 0 nvm base address calibration and auxillary space nvm main address space addresses are word addresses pw-1 pw 2^21 2^21+aw 0 nvm base address eeprom allocation program allocation nvm memory address space pw-1 boot allocation pw-1-(eeprom rows) x wr (bootprot rows) x wr pw-(eeprom rows) x wr (bootprot rows) x wr - 1
270 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 21-2. region size to lock or unlock a region, the lock region and unlock r egion commands are provided. writing one of these commands will temporarily lock/unlock the region containing the address loaded in the addr register. addr can be written by software, or the automatically loaded value from a write operation can be used. the new setting will stay in effect until the next reset, or the setting can be changed again using the lock and unlock commands. the current status of the lock can be determined by reading the lock register. to change the default lock/unlock setting for a region, the user configuration section of the auxiliary space must be written using the write auxiliary page command. writing to the auxiliary space will take effect after the next reset. therefore, a boot of the device is needed for changes in the lock/unlock setting to take effect. see ?product mapping? on page 23 for auxiliary space address mapping. 21.6.4 command and data interface the nvm controller is addressable from the apb bus, while the nvm main addres s space is addressable from the ahb bus. read and automatic page write operations are performed by addressing the nvm main address space directly, while other operations such as manual page writes and row erase must be performed by issuing commands through the nvm controller. to issue a command, the ctrla.cmd bits must be wri tten along with the ctrla.cmdex value. when a command is issued, intflag.ready will be cleared until the command has completed. any commands written while intflag.ready is low will be ignored. read the ctrla register description for more details. the ctrlb register must be used to control the power reduction mode, read wait states and the write mode. 21.6.4.1 nvm read reading from the nvm main address space is performed via the ahb bus by addressing the nvm main address space or auxiliary address space directly. read data is available af ter the configured number of read wait states (ctrlb.rws) set in the nvm controller. the number of cycles data are delayed to the ahb bus is determined by the read wait states. examples of using zero and one wait states are shown in figure 21-5 . memory size, in kbytes region size, in kbytes 256 16 128 8 64 4 32 2
271 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 21-5. read wait state examples 21.6.4.2 nvm write the nvm controller requires that an erase must be done before programming. the entire nvm main address space can be erased by a debugger chip erase command. alternatively, rows can be individually erased by the erase row command. after programming, the region that the page resides in can be locked to prevent spurious write or erase sequences. locking is performed on a per-region basis, and so locking a region locks all pages inside the region. data to be written to the nvm block are first written and stored in an internal buffer called the page buffer. the page buffer contains hw half words. writes to the page buffer must be 16 or 32 bits. 8-bit writes to the page buffer is not allowed, and will cause a system exception. writing to the nvm block via the ahb bus is performed by a load operation to the page buffer. for each ahb bus write, the address is stored in the addr register. after the page buffer has been loaded with the required number of words, the page can be written to the addressed location by setting cmd to write page and setting the key value to cmdex. the load bit in the status register indicates whether the page buffer has been loaded or not. before writing the page to memory, the accessed row must be erased. by default, automatic page writes are enabled (manw=0). this will trigger a write operation to the page addressed by addr when the last location of the page is written. because the address is automatically stored in addr duri ng the i/o bus write operation, the last given address will be present in the addr register. there is no need to load the addr register manually, unless a different page in memory is to be written. procedure for manual page writes (manw=1) the row to be written must be erased before the write command is given. z write to the page buffer by addressing the nvm main address space directly z write the page buffer to memory: cmd=write page and cmdex z the ready bit in the intflag register will be low while programming is in progress, and access through the ahb will be stalled procedure for automatic page writes (manw=0) the row to be written must be erased before the last write to the page buffer is performed. note that partially written pages must be written with a manual write. z write to the page buffer by addressing the nvm main address space directly. ? rd 0 rd 1 idle data 0 data 1 1 wait state rd 0 rd 1 idle data 0 data 1 0 wait states ahb command ahb slave ready ah b slave d ata ahb command ahb slave ready ahb slave data
272 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z when the last location in the page buffer is written, the page is automatically written to nvm main address space. z intflag.ready will be zero while programming is in progress and access through the ahb will be stalled. 21.6.4.3 page buffer clear the page buffer is automatically cleared to all ones after a page write is performed. if a partial page has been written and it is desired to clear the contents of the page buffer, the page buffer clear command can be used. 21.6.4.4 erase row before a page can be written, the row that contains the page must be erased. the erase row command can be used to erase the desired row. erasing the row sets all bits to one. if the row resides in a region that is locked, the erase will not be performed and the lock error bit in the stat us register (status.locke) will be set. procedure for erase row z write the address of the row to erase addr. any address within the row can be used. z issue an erase row command. 21.6.4.5 lock and unlock region these commands are used to lock and unlock regions as detailed in section ?region lock bits? on page 269 . 21.6.4.6 set and clear power reduction mode the nvm controller and block can be taken in and out of power reduction mode through the set and clear power reduction mode commands. when the nvm controller and blo ck are in power reduction mode, the power reduction mode bit in the status register (status.prm) is set. 21.6.5 user row table 21-3. user row organization the boot loader resides in the main array starting at offset zero. the allocated boot loader section is protected against write. bit position name usage 2:0 bootprot used to select one of eight different boot loader sizes (see table 21-4 .) rows included in the boot loader area can not be erased or programmed, except by a debugger chip erase. bootprot can be changed only when the security bit is cleared. 3 reserved 6:4 eeprom used to select one of eight different eeprom sizes. eeprom can be changed only when the security bit is cleared. 7 reserved 47:8 device dependant refer to ?non-volatile memory (nvm) user row mapping? on page 25 . 63:48 lock region lock bits.
273 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 21-4. boot loader size the eeprom bits indicates the eeprom size according to the table . eeprom resides in the upper rows of the nvm main address space and are writable, regardless of the region lock status. 21.6.6 security bit the security bit allows the entire chip to be locked from external access for code security. the security bit can be written by a dedicated command, set security bit (ssb). once set, the only way to clear the security bit is through a debugger chip erase command. after issuing the ssb command, the proge error bit can be checked. refer to ?dsu ? device service unit? on page 41 for details. 21.6.7 cache the nvm controller cache reduces the device power consum ption and improves system performance when wait states are required. it is a direct-mapped cache that implements 8 lines of 64 bits (i.e., 64 bytes). nvm controller cache can be enabled by writing a zero in the cachedis bit in the ctrl b register (ctrlb.cachedis). cache can be configured to three different modes using the readmode bit group in the ctrlb register. refer to ctrlb register description for more details. the invall command can be issued through the ctrla register to invalidate all cache lines. commands affecting nvm content automatically invalidate cache lines. bootprot [2:0] rows protected by bootprot boot size in bytes 7 none 0 6 2 512 5 4 1024 4 8 2048 3 16 4096 2 32 8192 1 64 16384 0 128 32768 table 21-5. eeprom size eeprom[2:0] rows allocated to eeprom eeprom size in bytes 7 none 0 6 1 256 5 2 512 4 4 1024 3 8 2048 2 16 4096 1 32 8192 0 64 16384
274 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 21.7 register summary offset name bit pos. 0x00 ctrla 7:0 cmd[6:0] 0x01 15:8 cmdex[7:0] 0x2 reserved 0x3 reserved 0x04 ctrlb 7:0 manw rws[3:0] 0x05 15:8 sleepprm[1:0] 0x06 23:16 cachedis readmode[1:0] 0x07 31:24 0x08 param 7:0 nvmp[7:0] 0x09 15:8 nvmp[15:8] 0x0a 23:16 psz[2:0] 0x0b 31:24 0x0c intenclr 7:0 error ready 0x0d reserved 0x0e reserved 0x0f reserved 0x10 intenset 7:0 error ready 0x11 reserved 0x12 reserved 0x13 reserved 0x14 intflag 7:0 error ready 0x15 reserved 0x16 reserved 0x17 reserved 0x18 status 7:0 nvme locke proge load prm 0x19 15:8 sb 0x1a reserved 0x1b reserved 0x1c addr 7:0 addr[7:0] 0x1d 15:8 addr[15:8] 0x1e 23:16 addr[21:16] 0x1f 31:24 0x20 lock 7:0 lock[7:0] 0x21 15:8 lock[15:8] 0x22 reserved 0x23 reserved
275 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 21.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each individual register des cription. please refer to the register access protection section and the pac chapter for details.
276 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 21.8.1 control a name: ctrla offset: 0x00 reset: 0x0000 property: write-protected z bits 15:8 ? cmdex: command execution this bit group should be written with the key value 0xa5 to enable the command written to cmd to be executed. if the bit group is written with a different key value, the write is not performed and the proge status bit is set. proge is also set if the a previously written command is not complete. the key value must be written at the same time as cmd. if a command is issued through the apb bus on the same cycle as an ahb bus access, the ahb bus access will be given priority. the command will then be executed when the nvm block and the ahb bus are idle. the ready status must be one when the command is issued. bit 0 of the cmdex bit group will read back as one until the command is issued. z bit 7 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 6:0 ? cmd: command these bits define the command to be executed when the cmdex key is written, as shown in table 21-6 . bit151413121110 9 8 cmdex[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 cmd[6:0] access r r/w r/w r/w r/w r/w r/w r/w reset00000000 table 21-6. command bit description cmd[4:0] group configuration description 0x00-0x01 - reserved 0x02 er erase row - erases the row addressed by the addr register. 0x03 - reserved 0x04 wp write page - writes the contents of t he page buffer to the page addressed by the addr register. 0x05 ear erase auxiliary row - erases the auxiliary row addressed by the addr register. this command can be given only when the security bit is not set and only to the user configuration row.
277 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 0x06 wap write auxiliary page - writes the contents of the page buffer to the page addressed by the addr register. this command can be given only when the security bit is not set and only to the user configuration row. 0x07-0x3f - reserved 0x40 lr lock region - locks the region containing the address location in the addr register. 0x41 ur unlock region - unlocks the region containing the address location in the addr register. 0x42 sprm sets the power reduction mode. 0x43 cprm clears the power reduction mode. 0x44 pbc page buffer clear - clears the page buffer. 0x45 ssb set security bit - sets the security bit by writing 0x00 to the first byte in the lockbit row. 0x46 invall invalidates all cache lines. 0x46-0x7f - reserved table 21-6. command bit description (continued) cmd[4:0] group configuration description
278 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 21.8.2 control b name: ctrlb offset: 0x04 reset: 0x00000000 property: write-protected z bits 31:19 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 18 ? cachedis: cache disable this bit is used to disable the cache. 0: the cache is enabled. 1: the cache is disabled. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 cachedis readmode[1:0] access r r r r r r/w r/w r/w reset00000000 bit151413121110 9 8 sleepprm[1:0] accessrrrrrrr/wr/w reset00000000 bit76543210 manw rws[3:0] accessrrrrrrr/wr/w reset00000000
279 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bits 17:16 ? readmode: nvmctrl read mode z bits 15:10 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 9:8 ? sleepprm: power re duction mode during sleep indicates the power reduction mode during sleep. table 21-7. table 1-7. power reduction mode during sleep z bit 7 ? manw: manual write 0: writing to the last word in the page buffer will initiate a write operation to the page addressed by the last write operation. this includes writes to memory and auxiliary rows. 1: write commands must be issued through the cmd register. z bits 6:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 4:1 ? rws: nvm read wait states these bits give the number of wait states for a read operation. zero indicates zero wait states, one indicates one wait state, etc., up to 15 wait states. this register is initialized to 0 wait states. software can change this value based on the nvm access time and sys- tem frequency. z bit 0 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. readmode name description 0x0 no_miss_penalty the nvm controller (cache system) do es not insert wait states on a cache miss. gives the best system performance. 0x1 low_power reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. this mode may not be relevant if cpu performance is r equired, as the application will be stalled and may lead to increase run time. 0x2 deterministic the cache system ensure s that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. this mode can be used for real-time applications that require deterministic execution timings. 0x3 reserved sleepprm[1:0] name description 0x0 wakeonaccess nvm block enters low-power mode when entering sleep. nvm block exits low-power mode upon first access. 0x1 wakeupinstant nvm block enters low-power mode when entering sleep. nvm block exits low-power mode when exiting sleep. 0x2 reserved 0x3 disabled auto power reduction disabled.
280 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 21.8.3 nvm parameter name: param offset: 0x08 reset: 0x000xxxxx property: ? z bits 31:19 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 18:16 ? psz: page size indicates the page size. not all device families will provide all the page sizes indicated in the table. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 psz[2:0] accessrrrrrrrr reset00000xxx bit151413121110 9 8 nvmp[15:8] accessrrrrrrrr resetxxxxxxxx bit76543210 nvmp[7:0] access r r r r r r r resetxxxxxxxx
281 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bits 15:0 ? nvmp: nvm pages indicates the number of pages in the nvm main address space. table 21-8. page size psz[2:0] name description 0x0 8 8 bytes 0x1 16 16 bytes 0x2 32 32 bytes 0x3 64 64 bytes 0x4 128 128 bytes 0x5 256 256 bytes 0x6 512 512 bytes 0x7 1024 1024 bytes
282 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 21.8.4 interrupt enable clear this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable set register (intenset). name: intenclr offset: 0x0c reset: 0x00 property: write-protected z bits 7:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? error: error interrupt enable writing a zero to this bit has no effect. writing a one to this bit clears the error interrupt enable. this bit will read as the current value of the error interrupt enable. z bit 0 ? ready: nvm ready interrupt enable writing a zero to this bit has no effect. writing a one to this bit clears the ready interrupt enable. this bit will read as the current value of the ready interrupt enable. bit76543210 error ready accessrrrrrrr/wr/w reset00000000
283 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 21.8.5 interrupt enable set this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear register (intenclr). name: intenset offset: 0x10 reset: 0x00 property: write-protected z bits 7:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? error: error interrupt enable writing a zero to this bit has no effect. writing a one to this bit sets the error interrupt enable. this bit will read as the current value of the error interrupt enable. z bit 0 ? ready: nvm ready interrupt enable writing a zero to this bit has no effect. writing a one to this bit sets the ready interrupt enable. this bit will read as the current value of the ready interrupt enable. bit76543210 error ready accessrrrrrrr/wr/w reset00000000
284 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 21.8.6 interrupt flag status and clear name: intflag offset: 0x14 reset: 0x00 property: ? z bits 7:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? error: error this flag is set on the occurrence of an nvme, locke or proge error. 0: no errors have been received since the last clear. 1: at least one error has occurred since the last clear. this bit can be cleared by writing a one to its bit location. z bit 0 ? ready: nvm ready 0: the nvm controller is busy programming or erasing. 1: the nvm controller is ready to accept a new command. bit76543210 error ready accessrrrrrrr/wr reset00000000
285 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 21.8.7 status name: status offset: 0x18 reset: 0x0x00 property: ? z bits 15:9 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 8 ? sb: security bit status 0: the security bit is inactive. 1: the security bit is active. z bits 7:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 4 ? nvme: nvm error 0: no programming or erase errors have been received from the nvm controller since this bit was last cleared. 1: at least one error has been registered from the nvm controller since this bit was last cleared. -this bit can be cleared by writing a one to its bit location. z bit 3 ? locke: lock error status 0: no programming of any locked lock region has happened since this bit was last cleared. 1: programming of at least one locked lock region has happened since this bit was last cleared. this bit can be cleared by writing a one to its bit location. z bit 2 ? proge: programming error status 0: no invalid commands or bad keywords were written in the nvm command register since this bit was last cleared. 1: an invalid command and/or a bad keyword was/were wri tten in the nvm command register since this bit was last cleared. this bit can be cleared by writing a one to its bit location. z bit 1 ? load: nvm page buffer active loading this bit indicates that the nvm page buffer has been loaded with one or more words. immediately after an nvm load has been performed, this flag is set, and it remains set until a page write or a page buffer clear (pbclr) com- mand is given. bit151413121110 9 8 sb accessrrrrrrrr reset0000000x bit76543210 nvme locke proge load prm access r r r r/w r/w r/w r/w r reset00000000
286 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 this bit can be cleared by writing a one to its bit location. z bit 0 ? prm: power reduction mode this bit indicates the current nvm power reduction stat e. the nvm block can be set in power reduction mode in two ways: through the command interface or automatically when entering sleep with sleepprm set accordingly. prm can be cleared in three ways: through ahb access to the nvm block, through the command interface (sprm and cprm) or when exiting sleep with sleepprm set accordingly. 0: nvm is not in power reduction mode. 1: nvm is in power reduction mode.
287 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 21.8.8 address name: addr offset: 0x1c reset: 0x00000000 property: write-protected z bits 31:22 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 21:0 ? addr: nvm address addr drives the hardware (16-bit) addr ess to the nvm when a command is executed using cmdex. this register is also automatically updated when writing to the page buffer. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 addr[21:16] access r r r/w r/w r/w r/w r/w r/w reset00000000 bit151413121110 9 8 addr[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 addr[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
288 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 21.8.9 lock section name: lock offset: 0x20 reset: 0xxxxx property: ? z bits 15:0 ? lock: region lock bits in order to set or clear these bits, the cmd register must be used. 0: the corresponding lock region is locked. 1: the corresponding lock region is not locked. bit151413121110 9 8 lock[15:8] accessrrrrrrrr resetxxxxxxxx bit76543210 lock[7:0] accessrrrrrrrr resetxxxxxxxx
289 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22. port 22.1 overview the port (port) controls the i/o pins of the microcontroller . the i/o pins are organized in a series of groups, collectively referred to as a line bundle, and each group can have up to 32 pins that can be configured and controlled individually or as a group. each pin may either be used for general-pur pose i/o under direct application control or assigned to an embedded device peripheral. when used for general-purpose i/o, each pin can be configured as input or output, with highly configurable driver and pull settings. all i/o pins have true read-modify-write (rmw) functionality when used for general-purpose i/o; the direction or the output value of one or more pins may be changed (set, reset or toggled) without unintentionally changing the state of any other pins in the same line bundle via a single, atomic 8-, 16- or 32-bit write. the port is connected to the high-speed bus matrix through an ahb/apb bridge. the pin direction, data output value and data input value registers may also be accessed using the low-latency cpu local bus (iobus; arm ? single-cycle i/o port). 22.2 features z selectable input and output configur ation individually for each pin z software-controlled multiplexing of peripheral functions on i/o pins z flexible pin configuration through a dedicated pin configuration register z configurable output driver and pull settings: z totem-pole (push-pull) z pull configuration z configurable input buffer and pull settings: z internal pull-up or pull-down z input sampling criteria z input buffer can be disabled if not needed for lower power consumption z read-modify-write support for pin configuration, output value and pin direction
290 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.3 block diagram figure 22-1. port block diagram 22.4 signal description refer to ?i/o multiplexing and considerations? on page 15 for details on the pin mapping for this peripheral. one signal can be mapped on several pins. 22.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 22.5.1 i/o lines the i/o lines of the port are mapped to pins of the physical device package according to a simple naming scheme. each line bundle of up to 32 pins is assigned a letter identifie r, starting with a, that monotonically increases through the alphabet for each subsequent line bundle. within each line bundle, each pin is assigned a numerical identifier according to its bit position. the resulting port pins are mapped as pxy, where x=a, b, c,? and y=00, 01, ?, 31 to uniquely identify each pin in the device, e.g., pa24, pc03, etc. each pin may have one or more peripheral multiplexer settings, which allow the pad to be routed internally to a dedicated peripheral function. when enabled, the selected peripheral is given control over the output state of the pad, as well as the ability to read the current physical pad state. refer to ?i/o multiplexing and considerations? on page 15 for details. device-specific configurations may result in some pins (and the corresponding pxy pin) not being implemented. portmux analog blocks peripherals digital controls of analog blocks analog pad connections i/o pads port line bundles ip line bundles peripheral mux select port control and status pad line bundles signal name type description pxy digital i/o general-purpose i/o pin y
291 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.5.2 power management during reset, all port lines are configured as inputs with input buffers, output buffers and pull disabled. if the port peripheral is shut down, the latches contained in the pad will retain their current configuration, such as the output value and pull settings. however, the port configuration registers and input synchronizers will lose their contents, and these will not be restored when port is power ed up again. the user must, therefore, reconfigure the port peripheral at power up to ensure it is in a well-defined state before use. the port will continue to operate in any sleep mode where the selected module source clock is running. 22.5.3 clocks the port bus clock (clk_port_apb) can be enabled and disabled in the power manager, and the default state of clk_port_apb can be found in the peripheral clock masking section in the ?pm ? power manager? on page 105 . the port is fed by two different clocks: a cpu main clock, which allows the cpu to access the port through the low- latency cpu local bus (iobus), and an apb clock, which is a divided clock of the cpu main clock and allows the cpu to acces the port registers through the high-speed matrix and the ahb/apb bridge. iobus accesses have priority over apb accesses. the latter must insert wait states in the event of concurrent port accesses. the port input synchronizers use the cpu main clock so that the resynchronization delay is minimized with respect to the apb clock. 22.5.4 dma not applicable. 22.5.5 interrupts not applicable. 22.5.6 events not applicable. 22.5.7 debug operation when the cpu is halted in debug mode, the port continues normal operation. if the port is configured in a way that requires it to be periodically serviced by the cpu through inte rrupts or similar, improper operation or data loss may result during debugging. 22.5.8 register access protection all registers with write-access are optionally write-pr otected by the peripheral access controller (pac). write-protection is denoted by the write-protected property in the register description. when the cpu is halted in debug mode, all wr ite-protection is automatically disabled. write-protection does not apply for accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details. 22.5.9 analog connections analog functions are connected directly between the analog blocks and the i/o pads using analog buses. however, selecting an analog peripheral function for a given pin will disable the corresponding digital features of the pad. 22.5.10 cpu local bus the cpu local bus (iobus) is an interface that connects the cpu directly to the port. it is a single-cycle bus interface, and does not support wait states. it supports byte, half word and word sizes.
292 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 this bus is generally used for low latency. the data direction (dir) and data output value (out) registers can be read, written, set, cleared or toggled using this bus, and the data input value (in) registers can be read. since the iobus cannot wait for in register resynchronizati on, the control register (ctrl) must be configured to enable continuous sampling of all pins that will need to be read via the iobus to prevent stale data from being read. 22.6 functional description figure 22-2. overview of the port 22.6.1 principle of operation the i/o pins of the device are controlled by reads and writes of the port peripheral registers. for each port pin, a corresponding bit in the data direction (dir) and data output value (out) registers are used to enable that pin as an output and to define the output state. the direction of each pin in a port bundle is configured via the dir register. if a bit in dir is written to one, the corresponding pin is configured as an output pin. if a bit in di r is written to zero, the corresponding pin is configured as an input pin. when the direction is set as output, the corresponding bit in the out register is used to set the level of the pin. if bit y of out is written to one, pin y is driven high. if bit y of out is written to zero, pin y is driven low. additional pin configuration can be set by writi ng to the pin configuration (pincfgy) registers. the data input value bit (in) is used to read the port pin with resynchronization to the port clock. by default, these input synchronizers are clocked only when an input value read is requested in order to reduce power consumption. input value can always be read, whether the pin is configured as input or output, except if digital input is disabled by writing a zero to the inen bit in the pin configuration registers (pincfgy). the port also allows peripheral functions to be connected to individual i/o pins by writing a one to the corresponding pmuxen bit in the pincfgy registers and by writing the ch osen selection to the peripheral multiplexing registers pulleny outy diry ineny portx pady 3.3v inen oe out pullen pady pull resistor pg ng input to other modules analog input/output in iny apb bus synchronizer port_mux ... ...
293 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 (pmuxn) for that pin. this will override the connection between the port and that i/o pin, and connect the selected peripheral line bundle to the pad instead of the port line bundle. each group of up to 32 pins is controlled by a set of registers, as described in figure 22-3 . this set of registers is duplicated for each group of pins, with increasing base addresses. figure 22-3. overview of the peripheral functions multiplexing 22.6.2 basic operation 22.6.2.1 initialization after reset, all standard-function device i/o pads are connected to the port with outputs tri-stated and input buffers disabled, even if no clocks are running. specific pins, such as the ones used for connection to a debugger, may be configured differently, as required by their special function. 22.6.3 basic operation each i/o pin y can be configured and accessed by reading or writing port registers. because port registers are grouped into sets of registers for each group of up to 32 pins, the base address of the register set for pin y is at byte address port + (y / 32) * 0x80. (y % 32) will be used as the index within that register set. to use pin y as an output, configure it as output by writing the (y % 32) bit in the dir register to one. to avoid disturbing the configuration of other pins in that group, this can also be done by writing the (y % 32) bit in the dirset register to one. the desired output value can be set by writing the (y % 32) bit to that value in register out. similarly, writing an outset bit to one will set the corres ponding bit in the out register to one, while writing an outclr bit to one will set it to zero, and writing an outtgl bit to one will toggle that bit in out. to use pin y as an input, configure it as input by writing the (y % 32) bit in the dir register to zero. to avoid disturbing the configuration of other pins in that group, this can also be done by writing the (y % 32) bit in dirclr register to one. the desired input value can be read from the (y % 32) bit in regi ster in as soon as the inen bit in the pin configuration register (pincfgy) is written to one. refer to ?i/o multiplexing and considerations? on page 15 for details on pin configuration. by default, the input synchronizer is clocked only when an in put read is requested, which will delay the read operation by two clk_port cycles. to remove that delay, the input synchronizers for each group of eight pins can be configured to port y pincfg port y periph line 0 port bit y pmuxen data+config periph line 1 periph line 15 port y pmux[3:0] port y pmux select portmux port y line bundle pad y pad y peripheral line bundles to be muxed to pad y port y peripheral mux enable 15 1 0 0 1 line bundle
294 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 be always active, but this comes at the expense of higher power consumption. this is controlled by writing a one to the corresponding samplingn bit group of the ct rl register, where n = (y % 32) / 8. to use pin y as one of the available peripheral functions for that pin, configure it by writing a one to the corresponding pmuxen bit of the pincfgy register. the pincfgy register for pin y is at byte offset (pincfg0 + (y % 32)). the peripheral function can be selected by writing to th e pmuxo or pmuxe bit group in the pmuxn register. the pmuxo/pmuxe bit group is at byte offset (pmux0 + (y % 32) / 2), in bits 3:0 if y is even and in bits 7:4 if y is odd. the chosen peripheral must also be configured and enabled. 22.6.4 i/o pin configuration the pin configuration register (pincfgy) is used for additional i/o pin configuration. a pin can be set in a totem-pole, open-drain or pull configuration. because pull configuration is done through the pin configurati on register, all intermediate port states during switching of pin direction and pin values are avoided. the i/o pin configurations are described further in this chapter, and summarized in table 22-1 . 22.6.4.1 pin configurations summary table 22-1. pin configurations summary 22.6.4.2 input configuration figure 22-4. i/o configuration - standard input dir inen pullen out configuration 0 0 0 x reset or analog i/o; all digital disabled 0 0 1 0 pull-down; input disabled 0 0 1 1 pull-up; input disabled 0 1 0 x input 0 1 1 0 input with pull-down 0 1 1 1 input with pull-up 1 0 x x output; input disabled 1 1 x x output; input enabled pullen dir ou t in inen pullen i nen dir 0 1 0
295 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 22-5. i/o configuration - input with pull note that when pull is enabled, the pu ll value is defined by the outx value. 22.6.4.3 totem-pole output when configured for totem-pole (push-pull) output, the pin is driven low or high according to the corresponding bit setting in the out register. in this configuration, there is no current limitation for sink or source other than what the pin is capabl e of. if the pin is configured for input, the pin will float if no external pull is connected. note, that enabling the output dri ver automatically disables pull. figure 22-6. i/o configuration - totem-pole output with disabled input figure 22-7. i/o configuration - totem-pole output with enabled input pullen dir ou t in inen pullen i nen dir 11 0 pullen dir ou t in inen pullen i nen dir 0 0 1 pullen dir ou t in inen pullen i nen dir 0 1 1
296 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 22-8. i/o configuration - output with pull 22.6.4.4 digital functionality disabled figure 22-9. i/o configuration - reset or analog i/o: digital output, input and pull disabled pullen dir ou t in inen pullen i nen dir 1 0 0 pullen dir ou t in inen pullen i nen dir 0 0 0
297 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.7 register summary the i/o pins are organized in groups with up to 32 pins. group 0 consists of the pa pins, group 1 the pb pins, etc. each group has its own set of registers. for example, the register address offset for the data direction (dir) register for group 0 (pa00 to pa31) is 0x00, while the register address offset for the dir register for group 1 (pb00 to pb31) is 0x80. offset name bit pos. 0x00 dir 7:0 dir[7:0] 0x01 15:8 dir[15:8] 0x02 23:16 dir[23:16] 0x03 31:24 dir[31:24] 0x04 dirclr 7:0 dirclr[7:0] 0x05 15:8 dirclr[15:8] 0x06 23:16 dirclr[23:16] 0x07 31:24 dirclr[31:24] 0x08 dirset 7:0 dirset[7:0] 0x09 15:8 dirset[15:8] 0x0a 23:16 dirset[23:16] 0x0b 31:24 dirset[31:24] 0x0c dirtgl 7:0 dirtgl[7:0] 0x0d 15:8 dirtgl[15:8] 0x0e 23:16 dirtgl[23:16] 0x0f 31:24 dirtgl[31:24] 0x10 out 7:0 out[7:0] 0x11 15:8 out[15:8] 0x12 23:16 out[23:16] 0x13 31:24 out[31:24] 0x14 outclr 7:0 outclr[7:0] 0x15 15:8 outclr[15:8] 0x16 23:16 outclr[23:16] 0x17 31:24 outclr[31:24] 0x18 outset 7:0 outset[7:0] 0x19 15:8 outset[15:8] 0x1a 23:16 outset[23:16] 0x1b 31:24 outset[31:24] 0x1c outtgl 7:0 outtgl[7:0] 0x1d 15:8 outtgl[15:8] 0x1e 23:16 outtgl[23:16] 0x1f 31:24 outtgl[31:24] 0x20 in 7:0 in[7:0] 0x21 15:8 in[15:8] 0x22 23:16 in[23:16] 0x23 31:24 in[31:24] 0x24 ctrl 7:0 sampling[7:0] 0x25 15:8 sampling[15:8] 0x26 23:16 sampling[23:16] 0x27 31:24 sampling[31:24]
298 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 0x28 wrconfig 7:0 pinmask[7:0] 0x29 15:8 pinmask[15:8] 0x2a 23:16 pullen inen pmuxen 0x2b 31:24 hwsel wrpincfg wrpmux pmux[3:0] 0x2c reserved 0x2d 0x2e 0x2f 0x30 pmux0 7:0 pmuxo[3:0] pmuxe[3:0] 0x31 pmux1 7:0 pmuxo[3:0] pmuxe[3:0] ??? 0x3e pmux14 7:0 pmuxo[3:0] pmuxe[3:0] 0x3f pmux15 7:0 pmuxo[3:0] pmuxe[3:0] 0x40 pincfg0 7:0 pullen inen pmuxen 0x41 pincfg1 7:0 pullen inen pmuxen ??? 0x5e pincfg30 7:0 pullen inen pmuxen 0x5f pincfg31 7:0 pullen inen pmuxen offset name bit pos.
299 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each individual register description. please refer to ?register access protection? on page 291 for details.
300 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.8.1 data direction name: dir offset: 0x00+x*0x80 [x=0..1] reset: 0x00000000 property: write-protected z bits 31:0 ? dir[31:0]: port data direction these bits set the data direction for the individual i/o pins in the port group. 0: the corresponding i/o pin in the group is configured as an input. 1: the corresponding i/o pin in the group is configured as an output. bit3130292827262524 dir[31:24] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit2322212019181716 dir[23:16] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit151413121110 9 8 dir[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 dir[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
301 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.8.2 data direction clear this register allows the user to set one or more i/o pins as an input, without doing a read-modify-write operation. changes in this register will also be reflected in the data direction (dir), data direction toggle (dirtgl) and data direction set (dirset) registers. name: dirclr offset: 0x04+x*0x80 [x=0..1] reset: 0x00000000 property: write-protected z bits 31:0 ? dirclr[31:0]: port data direction clear 0: the i/o pin direction is cleared. 1: the i/o pin direction is set. writing a zero to a bit has no effect. writing a one to a bit will clear the corresponding bit in the dir register, which configures the i/o pin as an input. bit 3130292827262524 dirclr[31:24] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 dirclr[23:16] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000 bit151413121110 9 8 dirclr[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 dirclr[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
302 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.8.3 data direction set this register allows the user to set one or more i/o pi ns as an output, without doing a read-modify-write operation. changes in this register will also be reflected in the data direction (dir), data direction toggle (dirtgl) and data direction clear (dirclr) registers. name: dirset offset: 0x08+x*0x80 [x=0..1] reset: 0x00000000 property: write-protected z bits 31:0 ? dirset[31:0]: port data direction set 0: the i/o pin direction is cleared. 1: the i/o pin direction is set. writing a zero to a bit has no effect. writing a one to a bit will set the corresponding bit in t he dir register, which configures the i/o pin as an output. bit 3130292827262524 dirset[31:24] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 dirset[23:16] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000 bit 151413121110 9 8 dirset[15:8] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000 bit76543210 dirset[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
303 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.8.4 data direction toggle this register allows the user to toggle the direction of one or more i/o pins, without doing a read-modify-write operation. changes in this register will also be reflected in the data dir ection (dir), data direction set (dirset) and data direction clear (dirclr) registers. name: dirtgl offset: 0x0c+x*0x80 [x=0..1] reset: 0x00000000 property: write-protected z bits 31:0 ? dirtgl[31:0]: po rt data direction toggle 0: the i/o pin direction is cleared. 1: the i/o pin direction is set. writing a zero to a bit has no effect. writing a one to a bit will toggle the corresponding bit in t he dir register, which reverses the direction of the i/o pin. bit 3130292827262524 dirtgl[31:24] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 dirtgl[23:16] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 dirtgl[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 dirtgl[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
304 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.8.5 data output value this register sets the data output drive value for the individual i/o pins in the port. name: out offset: 0x10+x*0x80 [x=0..1] reset: 0x00000000 property: write-protected z bits 31:0 ? out[31:0]: port data output value these bits set the logical output drive level of i/o pins configured as outputs via the data direction register (dir). for pins configured as inputs via the data direction regi ster (dir) with pull enabled via the pull enable register (pullen), these bits will set the input pull direction. 0: the i/o pin output is driven low, or the input is connected to an internal pull-down. 1: the i/o pin output is driven high, or the input is connected to an internal pull-up. bit 3130292827262524 out[31:24] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 out[23:16] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 out[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 out[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
305 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.8.6 data output value clear this register allows the user to set one or more output i/o pin drive levels low, without doing a read-modify-write operation. changes in this register will also be reflected in the data output value (out), data output value toggle (outtgl) and data output value set (outset) registers. name: outclr offset: 0x14+x*0x80 [x=0..1] reset: 0x00000000 property: write-protected z bits 31:0 ? outclr[31:0]: port data output value clear 0: the i/o pin output is driven low. 1: the i/o pin output is driven high. writing a zero to a bit has no effect. writing a one to a bit will clear the corresponding bit in the out register, which sets the output drive level low for i/o pins configured as outputs via the data direction regi ster (dir). for pins configured as inputs via the data direction register (dir) with pull enabled via the pull enable register (pullen), these bits will set the input pull direction to an internal pull-down. bit 3130292827262524 outclr[31:24] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 outclr[23:16] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 outclr[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 outclr[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
306 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.8.7 data output value set this register allows the user to set one or more output i/o pin drive levels high, without doing a read-modify-write operation. changes in this register will also be reflected in the data output value (out), data output value toggle (outtgl) and data output value clear (outclr) registers. name: outset offset: 0x18+x*0x80 [x=0..1] reset: 0x00000000 property: write-protected z bits 31:0 ? outset[31:0]: po rt data output value set 0: the i/o pin output is driven low. 1: the i/o pin output is driven high. writing a zero to a bit has no effect. writing a one to a bit will set the corresponding bit in the out register, which sets the output drive level high for i/o pins configured as outputs via the data direction register (dir). for pins configured as inputs via the data direc- tion register (dir) with pull enabled via the pull enable regist er (pullen), these bits will set the input pull direction to an internal pull-up. bit 3130292827262524 outset[31:24] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 outset[23:16] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 outset[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 outset[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
307 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.8.8 data output value toggle this register allows the user to toggle the drive level of one or more output i/o pins, without doing a read-modify-write operation. changes in this register will also be reflected in the data output value (out), data output value set (outset) and data output value clear (outclr) registers. name: outtgl offset: 0x1c+x*0x80 [x=0..1] reset: 0x00000000 property: write-protected z bits 31:0 ? outtgl[31:0]: port data output value toggle 0: the i/o pin output is driven low. 1: the i/o pin output is driven high. writing a zero to a bit has no effect. writing a one to a bit will toggle the corresponding bit in t he out register, which inverts the output drive level for i/o pins configured as outputs via the data direction regi ster (dir). for pins configured as inputs via the data direction register (dir) with pull enabled via the pull enabl e register (pullen), these bits will toggle the input pull direction. bit 3130292827262524 outtgl[31:24] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 outtgl[23:16] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 outtgl[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 76543210 outtgl[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
308 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.8.9 data input value name: in offset: 0x20+x*0x80 [x=0..1] reset: 0x00000000 property: - z bits 31:0 ? in[31:0]: port data input value these bits are cleared when the corresponding i/o pin input sampler detects a logical low level on the input pin. these bits are set when the corresponding i/o pin input sampler detects a logical high level on the input pin. bit 3130292827262524 in[31:24] accessrrrrrrrr reset00000000 bit 2322212019181716 in[23:16] accessrrrrrrrr reset00000000 bit 151413121110 9 8 in[15:8] accessrrrrrrrr reset00000000 bit76543210 in[7:0] accessrrrrrrrr reset00000000
309 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.8.10 control name: ctrl offset: 0x24+x*0x80 [x=0..1] reset: 0x00000000 property: write-protected z bits 31:0 ? sampling[31:0]: input sampling mode configures the input sampling functional ity of the i/o pin input samplers for pins configured as inputs via the data direction register (dir). 0: the i/o pin input synchronizer is disabled. 1: the i/o pin input synchronizer is enabled. the input samplers are enabled and disabled in sub-groups of eight. thus, if any pins within a byte request contin- uous sampling, all pins in that eight pin sub-group will be continuously sampled. bit 3130292827262524 sampling[31:24] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 2322212019181716 sampling[23:16] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit 151413121110 9 8 sampling[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 sampling[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
310 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.8.11 write configuration this write-only register is used to configure several pins simultaneously with the same configuration and/or peripheral multiplexing. in order to avoid the side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect. reading th is register always returns zero. name: wrconfig offset: 0x28+x*0x80 [x=0..1] reset: 0x00000000 property: write-protected z bit 31 ? hwsel: half-word select this bit selects the half-word field of a 32-pin group to be reconfigured in the atomic write operation. 0: the lower 16 pins of the port group will be configured. 1: the upper 16 pins of the port group will be configured. this bit will always read as zero. z bit 30 ? wrpincfg: write pincfg this bit determines whether the atomic write operation will update the pin configuration register (pincfgy) or not for all pins selected by the wrco nfig.pinmask and wrco nfig.hwsel bits. 0: the pincfgy registers of the selected pins will not be updated. 1: the pincfgy registers of the selected pins will be updated. writing a zero to this bit has no effect. bit3130292827262524 hwsel wrpincfg wrpmux pmux[3:0] accessww r wwwww reset00000000 bit2322212019181716 pullen inen pmuxen accessr w r wwwww reset00000000 bit 151413121110 9 8 pinmask[15:8] accesswwwwwwww reset00000000 bit76543210 pinmask[7:0] accesswwwwwwww reset00000000
311 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 writing a one to this bit updates the configuration of the selected pins with the written wrconfig.drvstr, wrconfig.slewlim, wrconfig.odrain, wrconfig.p ullen, wrconfig.inen, wrconfig.pmuxen and wrconfig.pinmask values. this bit will always read as zero. z bit 29 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 28 ? wrpmux: write pmux this bit determines whether the atomic write operation wi ll update the peripheral multiplexing register (pmuxn) or not for all pins selected by the wrconfig.pinmask and wrconfig.hwsel bits. 0: the pmuxn registers of the selected pins will not be updated. 1: the pmuxn registers of the selected pins will be updated. writing a zero to this bit has no effect. writing a one to this bit updates the pin multiplexer configuration of the selected pins with the written wrcon- fig.pmux value. this bit will always read as zero. z bits 27:24 ? pmux[3:0]: peripheral multiplexing these bits determine the new value written to the peripheral multiplexing register (pmuxn) for all pins selected by the wrconfig.pinmask and wrconfig.hwsel bi ts, when the wrconfig.wrpmux bit is set. these bits will always read as zero. z bits 23:19 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 18 ? pullen: pull enable this bit determines the new value written to pincfgy.pullen for all pins selected by the wrconfig.pinmask and wrconfig.hwsel bits when the wrconfig.wrpincfg bit is set. this bit will always read as zero. z bit 17 ? inen: input enable this bit determines the new value written to pincfgy.drvstr for all pins selected by the wrconfig.pinmask and wrconfig.hwsel bits when the wrconfig.wrpincfg bit is set. this bit will always read as zero. z bit 16 ? pmuxen: peripheral multiplexer enable this bit determines the new value written to pincfgy. pmuxen for all pins selected by the wrconfig.pin- mask and wrconfig.hwsel bits when the wrconfig.wrpincfg bit is set. this bit will always read as zero. z bits 15:0 ? pinmask[15:0]: pin mask for multiple pin configuration these bits select the pins to be configured within the half-word group selected by the wrconfig.hwsel bit. 0: the configuration of the corresponding i/o pin in the half-word group will be left unchanged. 1: the configuration of the corresponding i/o pin in the half-word pin group will be updated. these bits will always read as zero.
312 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.8.12 peripheral multiplexing n there are up to 16 peripheral multiplexing registers in each group, one for every set of two subsequent i/o lines. the n denotes the number of the set of i/o lines, while the m denotes the number of the group. name: pmuxn offset: 0x30+n*0x1+x*0x80 [n=0..15] [x=0..1] reset: 0x00 property: write-protected z bits 7:4 ? pmuxo[3:0]: peripheral multiplexing odd these bits select the peripheral function for odd-numbered pins (2*n + 1) of a port group, if the corresponding pincfgy.pmuxen bit is one. not all possible values for this selection may be valid. for more details, refer to ?i/o multiplexing and consider- ations? on page 15 . z bits 3:0 ? pmuxe[3:0]: peripheral multiplexing even these bits select the peripheral function for even-num bered pins (2*n) of a port group, if the corresponding pincfgy.pmuxen bit is one. not all possible values for this selection may be valid. for more details, refer to ?i/o multiplexing and consider- ations? on page 15 . bit76543210 pmuxo[3:0] pmuxe[3:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 value name description 0x0 a peripheral function a selected 0x1 b peripheral function b selected 0x2 c peripheral function c selected 0x3 d peripheral function d selected 0x4 e peripheral function e selected 0x5 f peripheral function f selected 0x6 g peripheral function g selected 0x7 h peripheral function h selected 0x8-0xf reserved
313 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 22.8.13 pin configuration y there are up to 32 pin configuration registers in each group, one for each i/o line. the y denotes the number of the i/o line, while the x denotes the number of the group. name: pincfgy offset: 0x40+y*0x1+x*0x80 [y=0..31] [x=0..1] reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? pullen: pull enable this bit enables the internal pull-up or pull-dow n resistor of an i/o pin configured as an input. 0: internal pull resistor is disabled, and the input is in a high-impedance configuration. 1: internal pull resistor is enabled, and the input is driven to a defined logic level in the absence of external input. z bit 1 ? inen: input enable this bit controls the input buffer of an i/o pin configured as either an input or output. 0: input buffer for the i/o pin is disabled, and the input value will not be sampled. 1: input buffer for the i/o pin is enabled, and the input value will be sampled when required. writing a zero to this bit disables the input buffer completely, preventing read-back of the physical pin state when the pin is configured as either an input or output. z bit 0 ? pmuxen: peripheral multiplexer enable this bit enables or disables the peripheral multiplexer sele ction set in the peripheral multiplexing register (pmuxn) to enable or disable alternative peripheral control over an i/o pin direction and output drive value. 0: the peripheral multiplexer selection is disabled, and the port registers control the direction and output drive value. 1: the peripheral multiplexer selection is enabled, and the selected peripheral controls the direction and output drive value. writing a zero to this bit allows the port to control t he pad direction via the data direction register (dir) and out- put drive value via the data output value register (out ). the peripheral multiplexer value in pmuxn is ignored. writing a one to this bit enables the peripheral selection in pmuxn to control the pad. in this configuration, the physical pin state may still be read from the data input value register (in) if pincfgy.inen is set. bit76543210 pullen inen pmuxen access r r/w r r/w r/w r/w r/w r/w reset00000000
314 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 23. evsys ? event system 23.1 overview the event system (evsys) allows autonomous, low-la tency and configurable communication between peripherals. several peripherals can be configured to emit and/or respond to signals known as events. the exact condition to generate an event, or the action taken upon receiving an event, is specific to each module. peripherals that respond to events are called event users. peripherals that emit event s are called event generators. a peripheral can have one or more event generators and can have one or more event users. communication is made without cpu intervention and without consuming system resources such as bus or ram bandwidth. this reduces the load on the cpu and other system resources, compared to a traditional interrupt-based system. 23.2 features z system for direct peripheral-to- peripheral communication and signaling z eight configurable event channels, where each channel can: z be connected to any event generator z provide a pure asynchronous, resynchronized or synchronous path z 59 event generators z 14 event users z configurable edge detector z peripherals can be event generators, event users or both z sleepwalking and interrupt for operation in low-power modes z software event generation z each event user can choose which channel to listen to
315 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 23.3 block diagram figure 23-1. event system block diagram 23.4 signal description not applicable. 23.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 23.5.1 i/o lines not applicable. 23.5.2 power management the evsys can be used to wake up the cpu from all sl eep modes, even if the clock used by the evsys channel and the evsys bus clock are disabled. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. in all power save modes where the clock for the evsys is stopped, the device can wake up the evsys clock. some event generators can generate an event when the system clock is stopped. the generic clock (gclk) for this channel will be restarted if the channel uses a synchronized path or a resynchronized path, without waking the system from sleep. the clock remains active only as long as necessary to handle the event. after the event has been handled, the clock will be turned off and the system will remain in the original sleep mode. this is known as sleepwalking. when an asynchronous path is used, there is no need for the clock to be activated for the event to be propagated to the user. on a software reset, all registers are set to their reset values and any ongoing events are canceled. 23.5.3 clocks the evsys bus clock (clk_evsys_apb) can be enabled and disabled in the power manager, and the default state of clk_evsys_apb can be found in the peripheral clock masking section in ?pm ? power manager? on page 105 . peripherals evsys channels user mux peripherals gclk generator events clock requests users events
316 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 each evsys channel has a dedicated generic clock (gclk_ evsys_x). these are used for detection and propagation of events for each channel. these clocks must be configured and enabled in the generic clock controller before using the evsys. please refer to ?gclk ? generic clock controller? on page 83 for details. 23.5.4 dma not applicable. 23.5.5 interrupts the interrupt request line is connected to the interrupt c ontroller. using the evsys interrupts requires the interrupt controller to be configured first. please refer to ?nested vector interrupt controller? on page 28 for details. 23.5.6 events not applicable. 23.5.7 debug operation when the cpu is halted in debug mode, the evsys continues normal operation. if the evsys is configured in a way that requires it to be periodically serviced by the cpu thr ough interrupts or similar, improper operation or data loss may result during debugging. 23.5.8 register access protection all registers with write-access are optionally write-protected by the peripheral access controller (pac), except the following register: z interrupt flag status and clear register ( intflag ) write-protection is denoted by the write-protected property in the register description. write-protection does not apply for accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details. 23.5.9 analog connections not applicable. 23.6 functional description 23.6.1 principle of operation event users are connected to multiplexers that have all available event channels as input. the multiplexer must be configured to select one of these channels. the channels c an be configured to route signals from any event generator, but cannot be connected to multiple event generators. 23.6.2 basic operation 23.6.2.1 initialization the peripheral that is to act as event generator should be c onfigured to be able to generate events. the peripheral to act as event user should be configured to handle incoming events. when this has been done, the event system is ready to be configured. the configuration must follow this order: 1. configure the event user by performing a single 16-bit write to the user multiplexer register (user) with: 1.1. the channel that is to be connected to a us er written to the channel bit group (user.channel) 1.2. the user to connect the channel to wr itten to the user bit group (user.user) 2. configure the channel by performing a single 32-bit write to the channel (channel) register with: 2.1. the channel to be configured written to t he channel selection bit group (channel.channel)
317 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 2.2. the path to be used written to the path selection bit group (channel.path) 2.3. the type of edge detection to use on the channel written to the edge selection bit group (channel.edgsel) 2.4. the event generator to be used written to the event generator bit group (channel.evgen) 23.6.2.2 enabling, disabling and resetting the evsys is always enabled. the evsys is reset by writing a one to the software reset bit in the control register (ctrl.swrst). all registers in the evsys will be reset to their initial state. refer to the ctrl register for details. 23.6.2.3 user multiplexer setup each user multiplexer is dedicated to one event user. a user multiplexer receives all event channel outputs and must be configured to select one of these channels. the user must always be configured before the channel is configured. a full list of selectable users can be found in the user multiplexer register (user) description. refer to table 23-6 for details. to configure a user multiplexer, the user r egister must be written in a single 16-bit write. it is possible to read out the configuration of a user by firs t selecting the user by writing to user.user using an 8-bit write and then performing a read of the user register. figure 23-2. user mux 23.6.2.4 channel setup the channel to be used with an event user must be configured with an event generator. the path of the channel should be configured, and when using a synchronous path or resynchr onized path, the edge selection should be configured. all these configurations are available in the channel register ( channel ). to configure a channel, the channel register must be written in a single, 32-bit write. it is possible to read out the configuration of a channel by first selecting the channel by writing to channel.channel using a, 8-bit write, and then performing a read of the channel register. user mux peripheral a peripheral b user.channel user_evt_x user_evt_y user_evt_z channel_evt_0 channel_evt_1 channel_evt_m
318 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 event generators the event generator is selected by writing to the event g enerator bit group in the channel register (channel.evgen). a full list of selectable generators can be found in the channel register description. refer to table 23-3 for details. the channels are not connected to any of the ev ent generators (channel.evgen = 0x00) by default. 23.6.2.5 channel path there are three different ways to propagate the event provided by an event generator: z asynchronous path z synchronous path z resynchronized path figure 23-3. channel the path is selected by writing to the path select ion bit group in the channel register (channel.path). asynchronous path when using the asynchronous path, the events are propagated from the event generator to the event user with no intervention from the event system. this means that if t he gclk_evsys_x for the channel used is inactive, the event will still be propagated to the user. events propagated in the asynchronous path cannot generate any in terrupts, and no channel status bits will indicate the state of the channel. no edge detection is available; this must be handled in the event user. when the event generator and the event user share the same generic clock, using the asynchronous path will propagate the event with the least amount of latency. channel.swevt channel m channel.evgen peripherals sleepwalking detector clock_request_m channel.path resync edge detection channel.edgsel channel_evt_m generators events sync async
319 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 synchronous path the synchronous path should be used when the event generator and the event channel share the same generic clock. if they do not share the same clock, a logic change from the event generator to the event channel might not be detected in the channel, which means that the event will not be propagated to the event user. when using the synchronous path, the channel is capable of generating interrupts. the channel status bits in the channel status register (chstatus) are also updated and available for use. if the generic clocks request bit in the control regist er (ctrl.gclkreq) is zero, the channel operates in sleepwalking mode and request the configured generic cl ock only when an event is to be propagated through the channel. if ctrl.gclkreq is one, the generic clock will always be on for the configured channel. resynchronized path the resynchronized path should be used when the event generator and the event channel do not share the same clock. when the resynchronized path is used, resynchronization of the event from the event generator is done in the channel. when the resynchronized path is used, the channel is capable of generating interrupts. the channel status bits in the channel status register (chstatus) are also updated and available for use. if the generic clocks request bit in the control regist er (ctrl.gclkreq) is zero, the channel operates in sleepwalking mode and request the configured generic cl ock only when an event is to be propagated through the channel. if ctrl.gclkreq is one, the generic clock will always be on for the configured channel. 23.6.2.6 edge detection when synchronous or resynchronized paths are used, edge detection must be used. the event system can perform edge detection in three different ways: z generate an event only on the rising edge z generate an event only on the falling edge z generate an event on rising and falling edges. edge detection is selected by writing to the edge select ion bit group in the channel register (channel.edgsel). if the generator event is a pulse, the both edges method must not be selected. use the rising edge or falling edge detection method, depending on the generator event default level. 23.6.2.7 the overrun channel x interrupt the overrun channel x interrupt flag in the interrupt flag status and clear register (intflag.ovrx) is set and the optional interrupt is generated in the following two cases: z at least one of the event users on channel x is not ready when a new event occurs z an event occurs when the previous event on channel x has not yet been handled by all event users intflag.ovrx will be set when using a synchronous or resynchronized path, but not when using an asynchronous path. 23.6.2.8 the event detect ed channel x interrupt the event detected channel x interrupt flag in the interrupt flag status and clear register (intflag.evdx) is set when an event coming from the event generator configured on channel x is detected. intflag.evdx will be set when using a synchronous and resynchronized path, but not when using an asynchronous path. 23.6.2.9 channel status the channel status register (chstatus) updates the st atus of the channels when a synchronous or resynchronized path is in use. there are two different status bits in chstatus for each of the available channels: the chstatus.chbusyx bit is set to one if an event on the corresponding channel x has not been handled by all event users connected to that channel.
320 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 the chstatus.usrrdyx bit is set to one if all event us ers connected to the corresponding channel x are ready to handle incoming events on that channel. 23.6.2.10 software event a software event can be initiated on a channel by writing a one to the software event bit in the channel register (channel.swevt) together with the channel bits (channe l.channel). this will generate a software event on the selected channel. the software event can be used for application debugging, and functions like any event generator. to use the software event, the event path must be configured to either a synchronous path or resynchronized path (channel.path = 0x0 or 0x1), edge detection must be configured to rising-edge det ection (channel.edgsel= 0x1) and the generic clock request bit must be set to one (ctrl.gclkreq=0x1). 23.6.3 interrupts the evsys has the following interrupt sources: z overrun channel x interrupt ( intflag ) z event detected channel x interrupt ( intflag ) each interrupt source has an interrupt flag associated with i t. the interrupt flag in the interrupt flag status and clear register (intflag) is set when the interrupt condition occu rs. each interrupt can be individually enabled by writing a one to the corresponding bit in the interrupt enable set regi ster (intenset), and disabled by writing a one to the corresponding bit in the interrupt enable clear register (int enclr). an interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the evsys is reset. see the intflag register for details on how to clear interrupt flags. the evsys has one common interrupt request line for all the interrupt sources. the user must read the intfla g register to determine which interrupt condition is present. note that interrupts must be globally enabled for interrupt requests to be generated. please refer to ?nested vector interrupt controller? on page 28 for details. 23.6.4 sleep mode operation the evsys can generate interrupts to wake up the device from any sleep mode.
321 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 23.7 register summary offset name bit pos. 0x00 ctrl 7:0 gclkreq swrst 0x01 reserved 0x02 reserved 0x03 reserved 0x04 channel 7:0 channel[7:0] 0x05 15:8 swevt 0x06 23:16 evgen[7:0] 0x07 31:24 edgsel[1:0] path[1:0] 0x08 user 7:0 user[7:0] 0x09 15:8 channel[7:0] 0x0a reserved 0x0b reserved 0x0c chstatus 7:0 usrrdy7 usrrdy6 usrrdy5 usrrdy4 usrrdy3 usrrdy2 usrrdy1 usrrdy0 0x0d 15:8 chbusy7 chbusy6 chbusy5 chbusy4 chbusy3 chbusy2 chbusy1 chbusy0 0x0e 23:16 0x0f 31:24 0x10 intenclr 7:0 ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 0x11 15:8 evd7 evd6 evd5 evd4 evd3 evd2 evd1 evd0 0x12 23:16 0x13 31:24 0x14 intenset 7:0 ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 0x15 15:8 evd7 evd6 evd5 evd4 evd3 evd2 evd1 evd0 0x16 23:16 0x17 31:24 0x18 intflag 7:0 ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 0x19 15:8 evd7 evd6 evd5 evd4 evd3 evd2 evd1 evd0 0x1a 23:16 0x1b 31:24
322 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 23.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each individual register description. please refer to ?register access protection? on page 316 and ?pac ? peripheral access controller? on page 31 for details. 23.8.1 control name: ctrl offset: 0x00 reset: 0x00 property: write-protected z bits 7:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 4 ? gclkreq: generic clock requests this bit is used to determine whether the generic clocks used for the different channels should be on all the time or only when an event needs the generic clock. events propagated trough asynchronous paths will not need a generic clock. 0: generic clock is requested and turned on only if an event is detected. 1: generic clock for a channel is always on. z bits 3:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? swrst: software reset writing a zero to this bit has no effect. writing a one to this bit resets all registers in the evsys to their initial state. writing a one to ctrl.swrst will always take precedence, meaning that all other writes in the same write-oper- ation will be discarded. bit76543210 gclkreq swrst access r r r r/w r r r w reset00000000
323 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 23.8.2 channel this register allows the user to configure the channel specif ied in the channel bit group. to write to this register, do a single, 32-bit write of all the configuration and channel selection data. to read from this register, first do an 8-bit writ e to the channel.channel bit group specifying the channel configuration to be read, and then read the channel register (channel). name: channel offset: 0x04 reset: 0x00000000 property: write-protected z bits 31:28 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 27:26 ? edgsel: edge detection selection these bits set the type of edge detection to be used on the channel. these bits must be written to zero when using the asynchronous path. bit3130292827262524 edgsel[1:0] path[1:0] access r r r r r/w r/w r/w r/w reset00000000 bit2322212019181716 evgen[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit151413121110 9 8 swevt accessrrrrrrrr/w reset00000000 bit76543210 channel[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
324 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 23-1. edge detection selection z bits 25:24 ? path: path selection these bits areused to chose which path will be used by the selected channel. table 23-2. path selection z bits 23:16 ? evgen: event generator these bits areused to choose the event generator to connect to the selected channel. value name description 0x0 no_evt_output no event output when using the resynchronized or synchronous path 0x1 rising_edge event detection only on the rising edge of the signal from the event generator 0x2 falling_edge event detection only on the falling edge of the signal from the event generator 0x3 both_edges event detection on rising and falling edges of the signal from the event generator value name description 0x0 synchronous synchronous path 0x1 resynchronized resynchronized path 0x2 asynchronous asynchronous path 0x3 - reserved table 23-3. event generator selection value event generator description 0x00 no event generator selected 0x01 rtc cmp0 compare 0 (mode 0 and 1) or alarm 0 (mode 2) 0x02 rtc cmp1 compare 1 0x03 rtc ovf overflow 0x04 rtc per0 period 0 0x05 rtc per1 period 1 0x06 rtc per2 period 2 0x07 rtc per3 period 3 0x08 rtc per4 period 4 0x09 rtc per5 period 5 0x0a rtc per6 period 6 0x0b rtc per7 period 7 0x0c eic extint0 external interrupt 0 0x0d eic extint1 external interrupt 1
325 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 0x0e eic extint2 external interrupt 2 0x0f eic extint3 external interrupt 3 0x10 eic extint4 external interrupt 4 0x11 eic extint5 external interrupt 5 0x12 eic extint6 external interrupt 6 0x13 eic extint7 external interrupt 7 0x14 eic extint8 external interrupt 8 0x15 eic extint9 external interrupt 9 0x16 eic extint10 external interrupt 10 0x17 eic extint11 external interrupt 11 0x18 eic extint12 external interrupt 12 0x19 eic extint13 external interrupt 13 0x1a eic extint14 external interrupt 14 0x1b eic extint15 external interrupt 15 0x1c tc0 ovf overflow/underflow 0x1d tc0 mc0 match/capture 0 0x1e tc0 mc1 match/capture 1 0x1f tc1 ovf overflow/underflow 0x20 tc1 mc0 match/capture 0 0x21 tc1 mc1 match/capture 1 0x22 tc2 ovf overflow/underflow 0x23 tc2 mc0 match/capture 0 0x24 tc2 mc1 match/capture 1 0x25 tc3 ovf overflow/underflow 0x26 tc3 mc0 match/capture 0 0x27 tc3 mc1 match/capture 1 0x28 tc4 ovf overflow/underflow 0x29 tc4 mc0 match/capture 0 0x2a tc4 mc1 match/capture 1 0x2b tc5 ovf overflow/underflow 0x2c tc5 mc0 match/capture 0 0x2d tc5 mc1 match/capture 1 0x2e tc6 ovf overflow/underflow table 23-3. event generator selection (continued) value event generator description
326 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bits 15:9 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 8 ? swevt: software event this bit is used to insert a software event on the channel selected by the channel.channel bit group. this bit must be written together with channel.channelusing a 16-bit write. writing a zero to this bit has no effect. writing a one to this bit will trigger a software event for the corresponding channel. this bit will always return zero when read. z bits 7:0 ? channel: channel selection these bits are used to select the channel to be set up or read from. 0x2f tc6 mc0 match/capture 0 0x30 tc6 mc1 match/capture 1 0x31 tc7 ovf overflow/underflow 0x32 tc7 mc0 match/capture 0 0x33 tc7 mc1 match/capture 1 0x34 adc resrdy result ready 0x35 adc winmon window monitor 0x36 ac comp0 comparator 0 0x37 ac comp1 comparator 1 0x38 ac win window 0 0x39 dac empty data buffer empty 0x3a ptc eoc end of conversion 0x3b ptc wcomp window comparator 0x3c-0xff reserved table 23-3. event generator selection (continued) value event generator description
327 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 23-4. channel selection value channel number 0x00 0 0x01 1 0x02 2 0x03 3 0x04 4 0x05 5 0x06 6 0x07 7 0x08-0xff reserved
328 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 23.8.3 user multiplexer this register is used to configure a specified event user. to write to this register, do a single, 16-bit write of all the configuration and event user selection data. to read from this register, first do an 8-bit write to the us er.user bit group specifying the event user configuration to be read, and then read user. name: user offset: 0x08 reset: 0x0000 property: write-protected z bits 15:8 ? channel: channel event selection these bits are used to select the channel to connect to the event user. please note that to select channel n, the value (n+1) must be written to the user.channel bit group. z bits 7:0 ? user: user multiplexer selection these bits select the event user to be configured with a channel, or the event user to read the channel value from. bit151413121110 9 8 channel[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 user[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 table 23-5. channel event selection value channel number 0x00 no channel output selected 0x01 0 0x02 1 0x03 2 0x04 3 0x05 4 0x06 5 0x07 6 0x08 7 0x09-0xff reserved
329 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 23-6. user multiplexer selection user[7:0] user multiplexer description path type 0x00 tc0 asynchronous, synchronous and resynchronized paths 0x01 tc1 asynchronous, synchronous and resynchronized paths 0x02 tc2 asynchronous, synchronous and resynchronized paths 0x03 tc3 asynchronous, synchronous and resynchronized paths 0x04 tc4 asynchronous, synchronous and resynchronized paths 0x05 tc5 asynchronous, synchronous and resynchronized paths 0x06 tc6 asynchronous, synchronous and resynchronized paths 0x07 tc7 asynchronous, synchronous and resynchronized paths 0x08 adc start adc start conversion asynchronous path only 0x09 adc sync flush adc asynchronous path only 0x0a ac comp0 start comparator 0 asynchronous path only 0x0b ac comp1 start comparator 1 asynchronous path only 0x0c dac start dac start conversion asynchronous path only 0x0d ptc stconv ptc start conversion asynchronous path only 0x0e-0xff reserved reserved
330 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 23.8.4 channel status name: chstatus offset: 0x0c reset: 0x000000ff property: ? z bits 31:16 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 15:8 ? chbusyx: channel busy x this bit is cleared when channel x is idle this bit is set if an event on channel x has not been handled by all event users connected to channel x. z bits 7:0 ? usrrdyx: user ready for channel x this bit is cleared when at least one of the event users connected to the channel is not ready. this bit is set when all event users connected to channel x are ready to handle incoming events on channel x. bit 3130292827262524 accessrrrrrrrr reset00000000 bit 2322212019181716 accessrrrrrrrr reset00000000 bit 151413121110 9 8 chbusy7 chbusy6 chbusy5 chbusy4 chbusy3 chbusy2 chbusy1 chbusy0 accessrrrrrrrr reset00000000 bit76543210 usrrdy7 usrrdy6 usrrdy5 usrrdy4 usrrdy3 usrrdy2 usrrdy1 usrrdy0 accessrrrrrrrr reset00000000
331 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 23.8.5 interrupt enable clear this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable set register (intenset). name: intenclr offset: 0x10 reset: 0x00000000 property: write-protected z bits 31:16 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 15:8 ? evdx: event detect ed channel x interrupt enable 0: the event detected channel x interrupt is disabled. 1: the event detected channel x interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the event detected channel x interrupt enable bit, which disables the event detected channel x interrupt. z bits 7:0 ? ovrx: overrun channel x interrupt enable 0: the overrun channel x interrupt is disabled. 1: the overrun channel x interrupt is enabled. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 accessrrrrrrrr reset00000000 bit151413121110 9 8 evd7 evd6 evd5 evd4 evd3 evd2 evd1 evd0 access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
332 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 writing a zero to this bit has no effect. writing a one to this bit will clear the overrun channel x interrupt enable bit, which disables the overrun channel x interrupt.
333 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 23.8.6 interrupt enable set this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear register (intenclr). name: intenset offset: 0x14 reset: 0x00000000 property: write-protected z bits 31:16 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 15:8 ? evdx: event detect ed channel x interrupt enable 0: the event detected channel x interrupt is disabled. 1: the event detected channel x interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the event detected channel x interrupt enable bit, which enables the event detected channel x interrupt. z bits 7:0 ? ovrx: overrun channel x interrupt enable 0: the overrun channel x interrupt is disabled. 1: the overrun channel x interrupt is enabled. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 accessrrrrrrrr reset00000000 bit151413121110 9 8 evd7 evd6 evd5 evd4 evd3 evd2 evd1 evd0 access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
334 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 writing a zero to this bit has no effect. writing a one to this bit will set the overrun channel x interrupt enable bit, which enables the overrun channel x interrupt.
335 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 23.8.7 interrupt flag status and clear name: intflag offset: 0x18 reset: 0x00000000 property: ? z bits 31:16 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 15:8 ? evdx: event detected channel x this flag is set on the next clk_evsys_apb cycle w hen an event is being propagated through the channel, and an interrupt request will be generated if intenclr/set.evdx is one. when the event channel path is asynchronous, the evdx interrupt flag will not be set. writing a zero to this bit has no effect. writing a one to this bit will clear the event detected channel n interrupt flag. z bits 7:0 ? ovrx: overrun channel x this flag is set on the next clk_evsys cycle after an overrun channel condition occurs, and an interrupt request will be generated if intenclr/set.ovrx is one. there are two possible overrun channel conditions: z one or more of the event users on channel x are not ready when a new event occurs z an event happens when the previous event on channel x has not yet been handled by all event users when the event channel path is asynchronous, the ovrx interrupt flag will not be set. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 accessrrrrrrrr reset00000000 bit151413121110 9 8 evd7 evd6 evd5 evd4 evd3 evd2 evd1 evd0 access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
336 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 writing a zero to this bit has no effect. writing a one to this bit will clear the overrun channel x interrupt flag.
337 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 24. sercom ? serial communication interface 24.1 overview the serial communication interface (sercom) can be configured to support a number of modes; i 2 c, spi and usart. once configured and enabled, all sercom resources are dedicated to the selected mode. the sercom serial engine consists of a transmitter and receiver, baud-rate generator and address matching functionality. it can be configured to use the internal generic clock or an external clock, making operation in all sleep modes possible. 24.2 features z combined interface configurable as one of the following: z i 2 c ? two-wire serial interface z smbus ? compatible. z spi ? serial peripheral interface z usart ? universal synchronous and asynchronous serial receiver and transmitter z single transmit buffer and double receive buffer z baud-rate generator z address match/mask logic z operational in all sleep modes 24.3 block diagram figure 24-1. sercom block diagram 24.4 signal description see the respective sercom mode chapters for details: z ?sercom usart ? sercom universal synchronous and asynchronous receiver and transmitter? on page 345 z ?sercom spi ? sercom serial peripheral interface? on page 369 z ?sercom i2c ? sercom inter-integrated circuit? on page 394 tx/rx data control/status mode n sercom baud/addr transmitter register interface serial engine receiver mode 0 mode 1 baud rate generator address match mode specific pad[3:0]
338 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 24.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 24.5.1 i/o lines using the sercom i/o lines requires the i/o pins to be configured using port configuration (port). refer to ?port? on page 289 for details. from figure 24-1 one can see that the sercom has four internal pads, pad[3:0]. the signals from i 2 c, spi and usart are routed through these sercom pads via a multiplexer. the configuration of the multiplexer is available from the different sercom modes. refer to t he mode specific chapters for details: z ?sercom usart ? sercom universal synchronous and asynchronous receiver and transmitter? on page 345 z ?sercom spi ? sercom serial peripheral interface? on page 369 z ?sercom i2c ? sercom inter-integrated circuit? on page 394 24.5.2 power management the sercom can operate in any sleep mode.sercom inte rrupts can be used to wake up the device from sleep modes. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. 24.5.3 clocks the sercom bus clock (clk_serco mx_apb) is enabled by default, and can be enabled and disabled in the power manager. refer to ?pm ? power manager? on page 105 for details. two generic clocks are used by the sercom: gclk_s ercomx_core and gclk_sercomx_slow. the core clock (gclk_sercomx_core) is required to clock the sercom while operating as a master, while the slow clock (gclk_sercomx_slow) is only required for certain functions. see specific mode chapters for details. these clocks must be configured and enabled in the generic cl ock controller (gclk) before using the sercom. refer to ?gclk ? generic clock controller? on page 83 for details. these generic clocks are asynchronous to the user interfac e clock (clk_sercomx_apb). due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. refer to ?synchronization? on page 344 for further details. 24.5.4 dma not applicable. 24.5.5 interrupts the interrupt request line is connected to the iinterrupt co ntroller. using the sercom interrupts requires the interrupt controller to be configured first. refer to ?nested vector interrupt controller? on page 28 for details. 24.5.6 events not applicable. 24.5.7 debug operation when the cpu is halted in debug mode, the sercom continues normal operation. if the sercom is configured in a way that requires it to be periodically serviced by the cpu through interrupts or similar, improper operation or data loss may result during debugging. the sercom can be forced to halt operation during debugging.
339 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 24.5.8 register access protection all registers with write-access are optionally write-protected by the peripheral access controller (pac), except the following registers: z interrupt flag status and clear register (intflag) z address register (addr) z data register (data) write-protection is denoted by the write-protection property in the register description. when the cpu is halted in debug mode, all write-protection is automatically disabled. refer to ?pac ? peripheral access controller? on page 31 for details. 24.5.9 analog connections not applicable. 24.6 functional description 24.6.1 principle of operation the basic structure of the sercom serial engine is shown in figure 24-2 . fields shown in capital letters are synchronous to the system clock and accessible by the cpu, wh ile fields with lowercase letters can be configured to run on the gclk_sercomx_core clock or an external clock. figure 24-2. serco m serial engine the transmitter consists of a single write buffer and a shift regi ster. the receiver consists of a two-level receive buffer and a shift register. the baud-rate generator is capable of r unning on the gclk_sercomx_core clock or an external clock. address matching logic is included for spi and i 2 c operation. transmitter baud rate ggenerator = = selectable internal clk (gclk) ext clk receiver address match baud rate generator tx shift register rx shift register rx buffer status baud tx data addr/addrmask rx data status 1/- /2- /16
340 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 24.6.2 basic operation 24.6.2.1 initialization the sercom must be configured to the desired mode by writ ing to the operating mode bits in the control a register (ctrla.mode). refer to figure 24-1 for details. table 24-1. sercom modes for further initialization information, see the respective sercom mode chapters. 24.6.2.2 enabling, disabling and resetting the sercom is enabled by writing a one to the enable bit in the control a register (ctr la.enable). the sercom is disabled by writing a zero to ctrla.enable. the sercom is reset by writing a one to the software reset bi t in the control a register (ctrla.swrst). all registers in the sercom, except dbgctrl, will be reset to their initial state, and the sercom will be disabled. refer to the ctrla register descriptions for details. 24.6.2.3 clock generation ? baud-rate generator the baud-rate generator, as shown in figure 24-3 , is used for internal clock generation for asynchronous and synchronous communication. the generated output frequency (f baud ) is determined by the b aud register (baud) setting and the baud reference frequency (f ref ). the baud reference clock is the serial engine clock, and it can be internal or external. for asynchronous operation, the /16 (divide-by-16) output is used when transmitting and the /1 (divide-by-1) output is used when receiving. for synchronous operation the /2 (divide-by-2) output is used. this functionality is automatically configured, depending on the selected operating mode. ctrla.mode description 0x0 usart with external clock 0x1 usart with internal clock 0x2 spi in slave operation 0x3 spi in master operation 0x4 i 2 c slave operation 0x5 i 2 c master operation 0x6-0x7 reserved
341 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 24-3. baud rate generator table 24-2 contains equations for calculating the baud rate (in bi ts per second) and for calculating the baud register value for each mode of operation. for asynchronous mode, the baud register value is 16 bi ts (0 to 65,535), while for synchronous mode, the baud register value is 8 bits (0 to 255). table 24-2. baud rate equations asynchronous mode baud value selection the formula given for f baud calculates the average frequency over 65,536 f ref cycles. although the baud register can be set to any value between 0 and 65,536, the values that will change the average frequency of f baud over a single frame are more constrained. the baud register values that will affect the average frequency over a single frame lead to an integer increase in the cycles per frame (cpf) where z d represent the data bits per frame z s represent the sum of start and first stop bits, if present base period selectable internal clk (gclk) ext clk ctrla.mode[0] 0 1 0 1 0 1 0 1 f ref clock recovery tx clk rx clk ctrla.mode /2 /8 /1 /2 /16 baud rate generator operating mode condition baud rate (bits per second) baud register value calculation asynchronous synchronous 16 f f ref baud ? ? ? ? ? ? ? = 536 , 65 1 16 baud f f ref baud ? ? ? ? ? ? ? ? ? = f f ref baud baud 16 1 536 , 65 2 f f ref baud ) 1 ( 2 + = baud f f ref baud 1 2 ? = f f baud ref baud ) ( s d cpf f f baud ref + =
342 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 24-3 shows the baud register value versus baud frequency at a serial engine frequency of 48mhz. this assumes a d value of 8 bits and an s value of 2 bits (10 bits, including start and stop bits). table 24-3. baud register va lue vs. baud frequency baud register value serial engine cpf f baud at 48mhz serial engine frequency (f ref ) 0 ? 406 160 3mhz 407 ? 808 161 2.981mhz 809 ? 1205 162 2.963mhz ... 65206 31775 15.11khz 65207 31871 15.06khz 65208 31969 15.01khz
343 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 24.6.3 additional features 24.6.3.1 address match and mask the sercom address match and mask feature is capable of matching one address with a mask, two unique addresses or a range of addresses, based on the mode selected. the match uses seven or eight bits, depending on the mode. address with mask an address written to the address bits in the address r egister (addr.addr) with a mask written to the address mask bits in the address register (addr.addrm ask) will yield an address match. all bits that are masked are not included in the match. note that setting the addr.addrmask to all zeros will match a single unique address, while setting addr.addrmask to all ones will result in all addresses being accepted. figure 24-4. address with mask two unique addresses the two addresses written to addr and addrmask will cause a match. figure 24-5. two unique addresses address range the range of addresses between and including addr.addr and addr.addrmask will caus e a match. addr.addr and addr.addrmask can be set to any two addresses, with addr.addr acting as the upper limit and addr.addrmask acting as the lower limit. figure 24-6. address range 24.6.4 dma operation not applicable. rx shift register addrmask addr == match addrmask rx shift register addr == match == addrmask rx shift register addr == match
344 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 24.6.5 interrupts interrupt sources are mode-specific. see the respective sercom mode chapters for details. each interrupt source has an interrupt flag associated with i t. the interrupt flag in the interrupt flag status and clear register (intflag) is set when the interrupt condition occu rs. each interrupt can be individually enabled by writing a one to the corresponding bit in the interrupt enable set regi ster (intenset), and disabled by writing a one to the corresponding bit in the interrupt enable clear register (int enclr). an interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the sercom is reset. see the register description for details on how to clear interrupt flags. the sercom has one common interrupt request line for all t he interrupt sources. the user must read the intflag register to determine which interrupt condition is present. note that interrupts must be globally enabled for interrupt requests to be generated. refer to ?nested vector interrupt controller? on page 28 for details. 24.6.6 events not applicable. 24.6.7 sleep mode operation the peripheral can operate in any sleep mode where the selected serial clock is running. this clock can be external or generated by the internal baud-rate generator. the sercom interrupts can be used to wake up the device from sleep modes. refer to the different sercom mode chapters for details. 24.6.8 synchronization due to the asynchronicity between clk_sercomx_ap b and gclk_sercomx_core, some registers must be synchronized when accessed. a register can require: z synchronization when written z synchronization when read z synchronization when written and read z no synchronization when executing an operation that requires synchronization, the synchronization busy bit in the status register (status.syncbusy) will be set immediately, and cleared when synchronization is complete. the synchronization ready interrupt can be used to signal when synchronization is complete. if an operation that requires synchronization is executed wh ile status.syncbusy is one, the bus will be stalled. all operations will complete successfully, but the cpu will be stalled and interrupts will be pending as long as the bus is stalled.
345 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 25. sercom usart ? sercom universa l synchronous and asynchronous receiver and transmitter 25.1 overview the universal synchronous and asynchronous receiver and transmitter (usart) is one of the available modes in the serial communication interface (sercom). refer to ?sercom ? serial communication interface? on page 337 for details. the usart uses the sercom transmitter and receiver configured as shown in figure 25-1 . fields shown in capital letters are synchronous to the clk_sercomx_apb and accessible by the cpu, while fields with lowercase letters can be configured to run on the internal generic clock or an external clock. the transmitter consists of a single write buffer, a shift regi ster and control logic for handling different frame formats. the write buffer allows continuous data transmission without any delay between frames. the receiver consists of a two-level receive buffer and a shift register. status information for the received data is available for error checking. data and clock recovery units ensure robust synchronization and noise filtering during asynchronous data reception. 25.2 features z full-duplex operation z asynchronous (with clock reconstruction) or synchronous operation z internal or external clock source for asynchronous and synchronous operation z baud-rate generator z supports serial frames with 5, 6, 7, 8 or 9 data bits and 1 or 2 stop bits z odd or even parity generation and parity check z selectable lsb- or msb-first data transfer z buffer overflow and frame error detection z noise filtering, including false start-bit detection and digital low-pass filter z can operate in all sleep modes z operation at speeds up to half the system clock for internally generated clocks z operation at speeds up to the system clock for externally generated clocks
346 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 25.3 block diagram figure 25-1. usart block diagram 25.4 signal description please refer to ?i/o multiplexing and considerations? on page 15 for details on the pin mapping for this peripheral. one signal can be mapped on several pins. 25.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 25.5.1 i/o lines using the usart?s i/o lines requires the i/o pins to be configured using port configuration (port). refer to ?port? on page 289 for details. when the sercom is used in usart mode, the pins should be configured according to table 25-1 . if the receiver or transmitter is disabled, these pins can be used for other purposes. table 25-1. usart pin configuration txd rxd xck rx shift register tx data tx shift register rx buffer rx data status status baud baud rate generator internal clk (gclk) /1 - /2 - /16 signal name type signal name type description pad[3:0] digital i/o general sercom pins pin pin configuration txd output rxd input xck output or input
347 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 the combined configuration of port and the transmit data pinout and receive data pinout bit groups (refer to the control a register description) will define the physical position of the usart signals in table 25-1 . 25.5.2 power management the usart can continue to operate in any sleep mode w here the selected source clock is running. the usart interrupts can be used to wake up the device from sleep m odes. the events can trigger other operations in the system without exiting sleep modes. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. 25.5.3 clocks the sercom bus clock (clk_sercomx _apb, where x represents the specific sercom instance number) can be enabled and disabled in the power manager, and the default state of clk_sercomx_apb can be found in the peripheral clock masking section in ?pm ? power manager? on page 105 . a generic clock (gclk_sercomx_core) is required to clo ck the sercomx_core. this clock must be configured and enabled in the generic clock controller before using the sercomx_core. refer to ?gclk ? generic clock controller? on page 83 for details. this generic clock is asynchronous to the bus clock (clk_serco mx_apb). due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. refer to ?synchronization? on page 353 for further details. 25.5.4 dma not applicable. 25.5.5 interrupts the interrupt request line is connected to the interrupt c ontroller. using the usart interrupts requires the interrupt controller to be configured first. refer to ?nested vector interrupt controller? on page 28 for details. 25.5.6 events not applicable. 25.5.7 debug operation when the cpu is halted in debug mode, the usart continues normal operation. if the usart is configured in a way that requires it to be periodically serviced by the cpu thr ough interrupts or similar, improper operation or data loss may result during debugging. the usart can be forced to halt operation during debugging. refer to dbgctrl for details. 25.5.8 register access protection all registers with write-access are optionally write-protected by the peripheral access controller (pac), except the following registers: z interrupt flag status and clear register (intflag) z status register (status) z data register (data) write-protection is denoted by the write-protection property in the register description. when the cpu is halted in debug mode, all writ e-protection is automatically disabled. write-protection does not apply for accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details.
348 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 25.5.9 analog connections not applicable. 25.6 functional description 25.6.1 principle of operation the usart uses three communication lines for data transfer: z rxd for receiving z txd for transmitting z xck for the transmission clock in synchronous operation usart data transfer is frame based, where a serial frame consists of: z 1 start bit z 5, 6, 7, 8 or 9 data bits z msb or lsb first z no, even or odd parity bit z 1 or 2 stop bits a frame starts with the start bit followed by one character of data bits. if enabled, the parity bit is inserted after the data bits and before the first stop bit. one frame can be directly followed by a new frame, or the communication line can return to the idle (high) state. figure 25-2 illustrates the possible frame formats. bits inside brackets are optional. figure 25-2. frame formats st start bit; always low (n) data bits; 0 to 8 p parity bit; odd or even sp stop bit; always high idle no transfers on the communication line; always high in this state 25.6.2 basic operation 25.6.2.1 initialization the following registers are enable-protected, meaning they can only be written when the usart is disabled (ctrl.enable is zero): z control a register (ctrla), except the e nable (enable) and software reset (swrst) bits z control b register (ctrlb), except the receiver enable (rxen) and transmi tter enable (txen) bits z baud register (baud) any writes to these registers when the usart is enabled or is being enabled (ctrl.enable is one) will be discarded. writes to these registers) while the peripheral is being disabled will be completed after the disabling is complete. before the usart is enabled, it must be configured, as outlined in the following steps: z usart mode with external or internal clock must be select ed first by writing 0x0 or 0x1 to the operating mode bit group in the control a register (ctrla.mode) 1 2 3 4 [5] [6] [7] [8] 0 st (idle) sp1 [sp2] (st/idle) [p] frame
349 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z communication mode (asynchronous or synchronous) must be selected by writing to the communication mode bit in the control a register (ctrla.cmode) z sercom pad to use for the receiver must be selected by writing to the receive data pinout bit group in the control a register (ctrla.rxpo) z sercom pads to use for the transmitter and external clock must be selected by writing to the transmit data pinout bit in the control a register (ctrla.txpo) z character size must be selected by writing to the character size bit group in the control b register (ctrlb.chsize) z msb- or lsb-first data transmission must be selected by wr iting to the data order bit in the control a register (ctrla.dord) z when parity mode is to be used, even or odd parity must be selected by writing to the parity mode bit in the control b register (ctrlb.pmode) and enabled by writing 0x1 to the frame form at bit group in the control a register (ctrla.form) z number of stop bits must be selected by writing to the stop bit mode bit in the control b register (ctrlb.sbmode) z when using an internal clock, the baud register (baud) must be written to generate the desired baud rate z the transmitter and receiver can be enabled by writing ones to the receiver enable and transmitter enable bits in the control b register (ctrlb.rxen and ctrlb.txen) 25.6.2.2 enabling, disabling and resetting the usart is enabled by writing a one to the enable bit in the control a register (ctrla.ena ble). the usart is disabled by writing a zero to ctrla.enable. the usart is reset by writing a one to the software reset bit in the control a register (ctrla.swrst). all registers in the usart, except dbgctrl, will be reset to their initial state, and the usart will be disabled. refer to the ctrla register for details. 25.6.2.3 clock generation and selection for both synchronous and asynchronous modes, the clock used for shifting and sampling data can be generated internally by the sercom baud-rate generator or suppli ed externally through the xck line. synchronous mode is selected by writing a one to the communication mode bit in the control a register (ctrla.cmode) and asynchronous mode is selected by writing a zero to ctrla.cmode. the internal clock source is selected by writing 0x1 to the operation mode bit group in the control a register (ctrla.mod e) and the external clock source is selected by writing 0x0 to ctrla.mode. the sercom baud-rate generator is configured as shown in figure 25-3 . when ctrla.cmode is zero, the baud-rate generator is automatically set to asynchronous mode and the 16-bit baud register value is used. when ctrla.cmode is one, the baud-rate generator is automatically set to syn chronous mode and the eight lsbs of the baud register are used. refer to ?clock generation ? baud-rate generator? on page 340 for details on configuring the baud rate.
350 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 25-3. clock generation synchronous clock operation when synchronous mode is used, the ctrla.mode bit group c ontrols whether the transmission clock (xck line) is an input or output. the dependency between the clock edges and data sampling or data change is the same for internal and external clocks. data input on the rxd pin is sampled at the opposite xck clock edge as data is driven on the txd pin. the clock polarity bit in the control a register (ctrla.c pol) selects which xck clock edge is used for rxd sampling and which is used for txd change. as shown in figure 25-4 , when ctrla.cpol is zero, the data will be changed on the rising xck edge and sampled on the falling xck edge. if ctrla.cpol is one, the data will be changed on the falling edge of xck and sampled on the rising edge of xck. figure 25-4. synchronous mode xck timing when the clock is provided through xck (ctrla.mode is 0x0) , the shift registers operate directly on the xck clock. this means that xck is not synchronize d with the system clock and, therefore, can operate at frequencies up to the system frequency. 25.6.2.4 data register the usart transmit data register (txd ata) and usart receive data register(r xdata) share the same i/o address, referred to as the data register (data). writing the data register will update the transmit data register. reading the data register will return the contents of the receive data register. xck baud rate generator base period /2 /2 /16 /1 ctrla.cmode 0 1 1 0 1 0 tx clk rx clk internal clk (gclk) 0 1 ctrla.mode[0] /8 sample rxd / txd xck ctrla.cpol=1 sample rxd / txd xck ctrla.cpol=0 change change
351 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 25.6.2.5 data transmission a data transmission is initiated by loading the data register with the data to be sent. the data in txdata is moved to the shift register when the shift register is empty and ready to send a new frame. when the shift register is loaded with data, one complete frame will be transmitted. the transmit complete interrupt flag in the interrupt fl ag status and clear register (intflag.txc) is set, and the optional interrupt is generated, when the entire frame in the shift register has been shifted out and there is no new data written to the data register. the data register should only be written when the data r egister empty flag in the interrupt flag status and clear register (intflag.dre) is set, which indicates t hat the register is empty and ready for new data. disabling the transmitter disabling the transmitter will not become effective until any ongoing and pending transmissions are completed, i.e., when the transmit shift register and txdata do not contain data to be transmitted. the transmitter is disabled by writing a zero to the transmitter enable bit in the control b register (ctrlb.txen). 25.6.2.6 data reception the receiver starts data reception when a valid start bit is det ected. each bit that follows the start bit will be sampled at the baud rate or xck clock, and shifted into the receive shift register until the first stop bit of a frame is received. when the first stop bit is received and a complete serial frame is pr esent in the receive shift register, the contents of the shift register will be moved into the two-level receive buffer. the receive complete interrupt flag in the interrupt flag status and clear register (intflag.r xc) is set, and the optional interrupt is generated. a second stop bit will be ignored by the receiver. the received data can be read by reading the data register. data should not be read unless the receive complete interrupt flag is set. disabling the receiver disabling the receiver by writing a zero to the receiver enabl e bit in the control b register (ctrlb.rxen) will flush the two-level receive buffer, and data from ongoing receptions will be lost. error bits the usart receiver has three error bits . the frame error (ferr), buffer overfl ow (bufovf) and parity error (perr) bits can be read from the status (status) register. u pon error detection, the corresponding bit will be set until it is cleared by writing a one to it. these bits are also automatically cleared when the receiver is disabled. asynchronous data reception the usart includes a clock recovery and data recovery unit for handling asynchronous data reception. the clock recovery logic is used to synchronize the incoming asynchronous serial frames at the rxd pin to the internally generated baud-rate clock. the data recovery logic samples and applies a low-pass filter to each incoming bit, thereby improving the noise immunity of the receiver. the asynchronous reception operational range depends on the accuracy of the internal baud-rate clock, the rate of the incoming frames and the frame size (in number of bits). asynchronous operational range the operational range of the receiver depends on the difference between the received bit rate and the internally generated baud rate. if the baud rate of an external transmitter is too high or too low compared to the internally generated baud rate, the receiver will not be able to synchronize the frames to the start bit. there are two possible sources for a mismatch in baud rate. the reference clock will alwa ys have some minor instability. in addition, the baud-rate generator can not always do an exact division of the reference clock frequency to get the baud rate desired. in this case, the baud register value should be selected to give the lowest possible error. refer to ?asynchronous mode baud value selection? on page 341 for details. recommended maximum receiver baud-rate errors for vari ous character sizes are shown in the table below.
352 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 25-2. asynchronous receiver error the recommended maximum receiver baud-rate error assume s that the receiver and transmitter equally divide the maximum total error. the following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate: where: z dis the sum of character size and parity size (d = 5 to 10 bits) z r slow is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate z r fast is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate 25.6.3 additional features 25.6.3.1 parity even or odd parity can be selected for error checking by writing 0x1 to the frame format bit group in the control a register (ctrla.form). if even parity is selected by writing a zero to the parity mode bit in the control b register (ctrlb.pmode), the parity bit of the outgoing frame is set to one if the number of data bits that are one is odd (making the total number of ones even). if odd parity is selected by wr iting a one to ctrlb.pmode, the parity bit of the outgoing frame is set to one if the number of data bits that are one is even (making the total number of ones odd). when parity checking is enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit of the corresponding frame. if a parity error is detected, the parity error bit in the status register (status.perr) is set. 25.6.4 interrupts the usart has the following interrupt sources: z receive complete z transmit complete z data register empty each interrupt source has an interrupt flag associated with i t. the interrupt flag in the interrupt flag status and clear register (intflag) is set when the interrupt condition occu rs. each interrupt can be individually enabled by writing a one to the corresponding bit in the interrupt enable set regi ster (intenset), and disabled by writing a one to the corresponding bit in the interrupt enable clear register (int enclr). an interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt request remains active until the interrupt flag is d (data bits + parity) r slow (%) r fast (%) max total error (%) recommended max rx error (%) 5 94.12 107.69 +5.88/-7.69 +/-2.5 6 94.92 106.67 +5.08/-6.67 +/-2.0 7 95.52 105.88 +4.48/-5.88 +/-2.0 8 96.00 105.26 +4.00/-5.26 +/-2.0 9 96.39 104.76 +3.61/-4.76 +/-1.5 10 96.70 104.35 +3.30/-4.35 +/-1.5 6 ) 1 ( 16 ) 1 ( 16 + + + = d d r slow 8 ) 1 ( 16 ) 2 ( 16 + + + = d d r fast
353 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 cleared, the interrupt is disabled or the usart is reset. see the register description for details on how to clear interrupt flags. the usart has one common interrupt request line for all t he interrupt sources. the user must read intflag to determine which interrupt condition is present. note that interrupts must be globally enabled for interrupt requests to be generated. refer to ?nested vector interrupt controller? on page 28 for details. 25.6.5 events not applicable. 25.6.6 sleep mode operation when using internal clocking, writing the run in standby bi t in the control a register (ctrla.runstdby) to one will allow gclk_sercomx_core to be enabled in all sleep modes. any interrupt can wake up the device. when using external clocking, writing a one to ctrla.runstd by will allow the receive complete interrupt.to wake up the device. if ctrla.runstdby is zero, the inter nal clock will be disabled when any ongoing transfer is finished. a transfer complete interrupt can wake up the device. when using external clocking, this will be disconnected when any ongoing transfer is finished, and all reception will be dropped. 25.6.7 synchronization due to the asynchronicity between clk_sercomx_ap b and gclk_sercomx_core, some registers must be synchronized when accessed. a register can require: z synchronization when written z synchronization when read z synchronization when written and read z no synchronization when executing an operation that requires synchronization, the synchronization busy bit in the status register (status.syncbusy) will be set immediately, and cleared when synchronization is complete. if an operation that requires synchronization is executed wh ile status.syncbusy is one, the bus will be stalled. all operations will complete successfully, but the cpu will be stalled and interrupts will be pending as long as the bus is stalled. the following bits need synchronization when written: z software reset bit in the control a register (ctrla.swrst) z enable bit in the control a register (ctrla.enable) z receiver enable bit in the co ntrol b register (ctrlb.rxen) z transmitter enable bit in the control b register (ctrlb.txen) ctrlb.rxen and ctrlb.txen behave somewhat different ly than described above. refer to ctrlb register description for details. synchronization is denoted by the write-synchronized property in the register description.
354 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 25.7 register summary offset name bit pos. 0x00 ctrla 7:0 runstdby mode[2:0] enable swrst 0x01 15:8 0x02 23:16 rxpo[1:0] txpo 0x03 31:24 dord cpol cmode form[3:0] 0x04 ctrlb dbgctrl 7:0 sbmode chsize[2:0] 0x05 15:8 pmode 0x06 23:16 rxen txen 0x07 31:24 0x08 7:0 dbgstop 0x09 reserved 0x0a baud 7:0 baud[7:0] 0x0b 15:8 baud[15:8] 0x0c intenclr 7:0 rxc txc dre 0x0d intenset 7:0 rxc txc dre 0x0e intflag 7:0 rxc txc dre 0x0f reserved 0x10 status 7:0 bufovf ferr perr 0x11 15:8 syncbusy 0x12 reserved 0x13 reserved 0x14 reserved 0x15 reserved 0x16 reserved 0x17 reserved 0x18 data 7:0 data[7:0] 0x19 15:8 data[8] 0x1a reserved 0x1b reserved 0x1c reserved 0x1d reserved 0x1e reserved 0x1f reserved
355 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 25.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each individual register description. refer to ?register access protection? on page 347 for details. some registers require synchronization when read and/or written. synchronization is denoted by the synchronized property in each individual register description. refer to ?synchronization? on page 353 for details. some registers are enable-protected, meaning they can only be written when the usart is disabled. enable-protection is denoted by the enable-protected property in each individual register description. 25.8.1 control a name: ctrla offset: 0x00 reset: 0x00000000 property: enable-protected, write-protected, write-synchronized z bit 31 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. bit3130292827262524 dord cpol cmode form[3:0] access r r/w r/w r/w r/w r/w r/w r/w reset00000000 bit2322212019181716 rxpo[1:0] txpo access r r r/w r/w r r r r/w reset00000000 bit151413121110 9 8 accessrrrrrrrr reset00000000 bit76543210 runstdby mode[2:0] enable swrst access r/w r r r/w r/w r/w r/w r/w reset00000000
356 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bit 30 ? dord: data order this bit indicates the data order when a character is shifted out from the data register. 0: msb is transmitted first. 1: lsb is transmitted first. this bit is not synchronized. z bit 29 ? cpol: clock polarity this bit indicates the relationship between data output change and data input sampling in synchronous mode. this bit is not synchronized. table 25-3. clock polarity z bit 28 ? cmode: communication mode this bit indicates asynchronous or synchronous communication. 0: asynchronous communication. 1: synchronous communication. this bit is not synchronized. z bits 27:24 ? form[3:0]: frame format these bits define the frame format. these bits are not synchronized. table 25-4. frame format z bits 23:22 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 21:20 ? rxpo[1:0]: receive data pinout these bits define the receive data (rxd) pin configuration. these bits are not synchronized. cpol txd change rxd sample 0x0 rising xck edge falling xck edge 0x1 falling xck edge rising xck edge form[3:0] description 0x0 usart frame 0x1 usart frame with parity 0x2-0xf reserved
357 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bits 19:17 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 16 ? txpo: transmit data pinout this bit defines the transmit data (txd) and xck pin configurations. this bit is not synchronized. table 25-6. transmit data pinout z bits 15:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 7 ? runstdby: run in standby this bit defines the functionality in standby sleep mode. this bit is not synchronized. table 25-7. run in standby z bits 6:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 4:2 ? mode: operating mode these bits must be written to 0x0 or 0x1 to select the usart serial communication interface of the sercom. 0x0: usart with external clock. 0x1: usart with internal clock. these bits are not synchronized. table 25-5. receive data pinout rxpo[1:0] description 0x0 sercom_pad0 0x1 sercom_pad1 0x2 sercom_pad2 0x3 sercom_pad3 txpo txd pin location xck pin location (when applicable) 0x0 sercom_pad0 sercom_pad1 0x1 sercom_pad2 sercom_pad3 runstdby external clock internal clock 0x0 external clock is disconnected when ongoing transfer is finished. all reception is dropped. 0x1 genericclock is enabled in all sleep modes. any interrupt can wake up the device.
358 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bit 1 ? enable: enable 0: the peripheral is disabled or being disabled. 1: the peripheral is enabled or being enabled. due to synchronization, there is delay from writing ctrla.enable until the peripheral is enabled/disabled. the value written to ctrla.enable will read back immediat ely and the synchronization busy bit in the status regis- ter (status.syncbusy) will be se t. status.syncbusy is cleared when the operation is complete. this bit is not enable-protected. z bit 0 ? swrst: software reset 0: there is no reset operation ongoing. 1: the reset operation is ongoing. writing a zero to this bit has no effect. writing a one to this bit resets all registers in the serc om, except dbgctrl, to their initial state, and the ser- com will be disabled. writing a one to ctrla.swrst will always take precedence, meaning that all other writes in the same write-oper- ation will be discarded. due to synchronization, there is a delay from writing ctrla.swrst until the reset is complete. ctrla.swrst and status.syncbusy will both be cl eared when the reset is complete. this bit is not enable-protected.
359 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 25.8.2 control b name: ctrlb offset: 0x04 reset: 0x00000000 property: enable-protected, write-protected, write-synchronized z bits 31:18 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 17 ? rxen: receiver enable 0: the receiver is disabled or being enabled. 1: the receiver is enabled or will be enabled when the usart is enabled. writing a zero to this bit will disable the usart receiv er. disabling the receiver will flush the receive buffer and clear the ferr, perr and bufovf bits in the status register. writing a one to ctrlb.rxen when the usart is disabl ed will set ctrlb.rxen immediately. when the usart is enabled, ctrlb.rxen will be cleared, and status.syncb usy will be set and remain set until the receiver is enabled. when the receiver is enabled, ctrlb.rxen will read back as one. writing a one to ctrlb.rxen when the usart is enabled will set status.syncbusy, which will remain set until the receiver is enabled, and ctrlb.rxen will read back as one. this bit is not enable-protected. z bit 16 ? txen: transmitter enable 0: the transmitter is disabled or being enabled. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 rxen txen accessrrrrrrr/wr/w reset00000000 bit151413121110 9 8 pmode access r r r/w r r r r/w r reset00000000 bit76543210 sbmode chsize[2:0] access r r/w r r r r/w r/w r/w reset00000000
360 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 1: the transmitter is enabled or wil l be enabled when the usart is enabled. writing a zero to this bit will disable the usart transmitter. disabling the transmitter will not become effective until ongoing and pending transmissions are completed. writing a one to ctrlb.txen when the usart is disabled will set ctrlb.txen immediately. when the usart is enabled, ctrlb.txen will be cleared, and status.syncb usy will be set and remain set until the transmitter is enabled. when the transmitter is enabled, ctrlb.txen will read back as one. writing a one to ctrlb.txen when the usart is enabled will set status.syncbusy, which will remain set until the receiver is enabled, and ctrlb.txen will read back as one. this bit is not enable-protected. z bits 15:14 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 13 ? pmode: parity mode this bit selects the type of parity used when parity is enabled (ctrla.form is one). the transmitter will automat- ically generate and send the parity of the transmitted data bits within each frame. the receiver will generate a parity value for the incoming data and parity bit, compare it to the parity mode and, if a mismatch is detected, sta- tus.perr will be set. 0: even parity. 1: odd parity. this bit is not synchronized. z bits 12:7 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. -- z bit 6 ? sbmode: stop bit mode this bit selects the number of stop bits transmitted. 0: one stop bit. 1: two stop bits. this bit is not synchronized. z bits 5:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 2:0 ? chsize[2:0]: character size these bits select the number of bits in a character.
361 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 these bits are not synchronized. table 25-8. character size chsize[2:0] description 0x0 8 bits 0x1 9 bits 0x2-0x4 reserved 0x5 5 bits 0x6 6 bits 0x7 7 bits
362 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 25.8.3 debug control name: dbgctrl offset: 0x08 reset: 0x00 property: write-protected z bits 7:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? dbgstop: debug stop mode this bit controls the baud-rate generator functionality when the cpu is halted by an external debugger. 0: the baud-rate generator continues normal operati on when the cpu is halted by an external debugger. 1: the baud-rate generator is halted when the cpu is halted by an external debugger. bit76543210 dbgstop accessrrrrrrrr/w reset00000000
363 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 25.8.4 baud name: baud offset: 0x0a reset: 0x0000 property: enable-protected, write-protected z bits 15:0 ? baud: baud value these bits control the clock generation, as described in the sercom baud rate section. bit151413121110 9 8 baud[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 baud[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
364 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 25.8.5 interrupt enable clear this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable setregister (intenset) . name: intenclr offset: 0x0c reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? rxc: receive comp lete interrupt enable 0: receive complete interrupt is disabled. 1: receive complete interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the receive complete in terrupt enable bit, which disables the receive complete interrupt. z bit 1 ? txc: transmit co mplete interrupt enable 0: transmit complete interrupt is disabled. 1: transmit complete interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the transmit complete interrupt enable bit, which disables the receive complete interrupt. z bit 0 ? dre: data register empty interrupt enable 0: data register empty interrupt is disabled. 1: data register empty interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the data register empty interrupt enable bit, which disables the data register empty interrupt. bit76543210 rxc txc dre access r r r r r r/w r/w r/w reset00000000
365 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 25.8.6 interrupt enable set this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear register (intenclr) . name: intenset offset: 0x0d reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? rxc: receive comp lete interrupt enable 0: receive complete interrupt is disabled. 1: receive complete interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the receive complete interrupt enable bit, which enables the receive complete interrupt. z bit 1 ? txc: transmit co mplete interrupt enable 0: transmit complete interrupt is disabled. 1: transmit complete interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the transmit complete interrupt enable bit, which enables the transmit complete interrupt. z bit 0 ? dre: data register empty interrupt enable 0: data register empty interrupt is disabled. 1: data register empty interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the data register empty interrupt enable bit, which enables the data register empty interrupt. bit76543210 rxc txc dre accessrrrrrr/wr/wr/w reset00000000
366 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 25.8.7 interrupt flag status and clear name: intflag offset: 0x0e reset: 0x00 property: z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z -- bit 2 ? rxc: receive complete this flag is cleared by reading the data regist er (data) or by disabling the receiver. this flag is set when there are unread data in data. writing a zero to this bit has no effect. writing a one to this bit has no effect. z bit 1 ? txc: transmit complete this flag is cleared by writing a one to it or by writing new data to data. this flag is set when the entire frame in the transmit sh ift register has been shifted out and there are no new data in data. writing a zero to this bit has no effect. writing a one to this bit will clear the flag. z bit 0 ? dre: data register empty this flag is cleared by writing new data to data. this flag is set when data is empty and ready to be written. writing a zero to this bit has no effect. writing a one to this bit has no effect. bit76543210 rxc txc dre accessrrrrrrr/wr reset00000000
367 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 25.8.8 status name: status offset: 0x10 reset: 0x0000 property: z bit 15 ? syncbusy: synchronization busy this bit is cleared when the synchronization of registers between the clock domains is complete. this bit is set when the synchronization of registers between clock domains is started. z bits 14:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? bufovf: buffer overflow reading this bit before reading the data register will indi cate the error status of the next character to be read. this bit is cleared by writing a one to the bit or by disabling the receiver. this bit is set when a buffer overflow condition is detected. a buffer overflow occurs when the receive buffer is full, there is a new character waiting in the receive shift register and a new start bit is detected. writing a zero to this bit has no effect. writing a one to this bit will clear it. z bit 1 ? ferr: frame error reading this bit before reading the data register will indi cate the error status of the next character to be read. this bit is cleared by writing a one to the bit or by disabling the receiver. this bit is set if the received character had a frame error, i.e., when the first stop bit is zero. writing a zero to this bit has no effect. writing a one to this bit will clear it. z bit 0 ? perr: parity error reading this bit before reading the data register will indi cate the error status of the next character to be read. this bit is cleared by writing a one to the bit or by disabling the receiver. this bit is set if parity checking is enabled (ctrla.form is one) and a parity error is detected. writing a zero to this bit has no effect. writing a one to this bit will clear it. bit151413121110 9 8 syncbusy access r/w r r r r r r r reset00000000 bit76543210 bufovf ferr perr access r r r r r r/w r/w r/w reset00000000
368 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 25.8.9 data name: data offset: 0x18 reset: 0x0000 property: - z bits 15:9 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 8:0 ? data[8:0]: data reading these bits will return the contents of the receive data register. the register should be read only when the receive complete interrupt flag bit in the interrupt flag status and clear register (intflag.rxcif) is set. the status bits in status should be read before reading th e data value in order to get any corresponding error. writing these bits will write the transmit data register. this register should be written only when the data register empty interrupt flag bit in the interrupt flag st atus and clear register (intflag.dreif) is set. bit151413121110 9 8 data[8] accessrrrrrrrr/w reset00000000 bit76543210 data[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
369 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26. sercom spi ? sercom seri al peripheral interface 26.1 overview the serial peripheral interface (spi) is one of the avail able modes in the serial communication interface (sercom). refer to ?sercom ? serial communication interface? on page 337 for details. the spi uses the sercom transmitter and receiver configured as shown in ?full-duplex spi master slave interconnection? on page 369 . each side, master and slave, depicts a separate spi containing a shift register, a transmit buffer and two receive buffers. in addition, the spi master uses the sercom baud-rate generator, while the spi slave can use the sercom address match logic. fields shown in capital letters are synchronous to clk_sercomx_apb and accessible by the cpu, while fields with lowercase letters are synchronous to the sck clock. 26.2 features z full-duplex, four-wire interface (miso, mosi, sck, _ss) z single-buffered transmitter, double-buffered receiver z supports all four spi modes of operation z single data direction operation allows alternate function on miso or mosi pin z selectable lsb- or msb-first data transfer z master operation: z serial clock speed up to half the system clock z 8-bit clock generator z slave operation: z serial clock speed up to the system clock z optional 8-bit address match operation z operation in all sleep modes 26.3 block diagram figure 26-1. full-duplex spi master slave interconnection 26.4 signal description refer to ?i/o multiplexing and considerations? on page 15 for details on the pin mapping for this peripheral. one signal can be mapped to one of several pins. shift register shift register master slave miso mosi sck _ss tx data rx buffer rx data tx data rx buffer rx data == addr/addrmask baud baud rate generator address match signal name type description pad[3:0] digital i/o general sercom pins
370 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 26.5.1 i/o lines using the sercom?s i/o lines requires the i/o pins to be configured using port configuration (port). refer to ?port? on page 289 for details. when the sercom is configured for spi operation, the pins should be configured according to table 26-1 . if the receiver is disabled, the data input pin can be used for other purposes. in master mode the slave select line (_ss) is controlled by software. table 26-1. spi pin configuration the combined configuration of port and the data in/data out and data out pinout bit groups in control a register will define the physical position of the spi signals in table 26-1 . 26.5.2 power management the spi can continue to operate in any sleep mode. the spi interrupts can be used to wake up the device from sleep modes. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. 26.5.3 clocks the sercom bus clock (clk_sercomx _apb) can be enabled and disabled in the power manager, and the default state of clk_sercomx_apb can be found in the peripheral clock masking section in the ?pm ? power manager? on page 105 . a generic clock (gclk_sercomx_core) is required to clo ck the spi. this clock must be configured and enabled in the generic clock controller before using the spi. refer to ?gclk ? generic clock controller? on page 83 for details. this generic clock is asynchronous to the bus clock (clk_serco mx_apb). due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. refer to ?synchronization? on page 377 for further details. 26.5.4 dma not applicable. 26.5.5 interrupts the interrupt request line is connected to the interrupt c ontroller. using the spi, interrupts requires the interrupt controller to be configured first. refer to ?nested vector interrupt controller? on page 28 for details. 26.5.6 events not applicable. pin master spi slave spi mosi output input miso input output sck output input _ss user defined output enable input
371 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.5.7 debug operation when the cpu is halted in debug mode, the spi continues normal operation. if the spi is configured in a way that requires it to be periodically serviced by the cpu through inte rrupts or similar, improper operation or data loss may result during debugging. the spi can be forced to halt operation during debugging. refer to the debug control (dbgctrl) register for details. 26.5.8 register access protection all registers with write-access are optionally write-protected by the peripheral access controller (pac), except the following registers: z interrupt flag clear and status register (intflag) z status register (status) z data register (data) write-protection is denoted by the write-protection property in the register description. when the cpu is halted in debug mode, all writ e-protection is automatically disabled. write-protection does not apply for accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details. 26.5.9 analog connections not applicable. 26.6 functional description 26.6.1 principle of operation the spi is a high-speed synchronous data transfer interface. it allows fast communication between the device and peripheral devices. the spi can operate as master or slave. as master, the spi in itiates and controls all data transactions. the spi is single buffered for transmitting and double buffered for receiving. when transmitting data, the data register can be loaded with the next character to be transmitted while the current transmission is in progress. for receiving, this means that the data is transferred to the two-level receive buffer upon reception, and the receiver is ready for a new character. the spi transaction format is shown in figure 26-2 , where each transaction can contai n one or more characters. the character size is configurable, and can be either 8 or 9 bits. figure 26-2. spi transaction format the spi master must initiate a transaction by pulling low the slave select line (_ss) of the desired slave. the master and slave prepare data to be sent in their respective shift regist ers, and the master generates the serial clock on the sck line. data are always shifted from master to slave on the master output, slave input line (mosi), and from slave to master on the master input, slave output line (miso). the master si gnals the end of the transaction by pulling the _ss line high. as each character is shifted out from the master, another character is shifted in from the slave. character transaction mosi/miso _ss character 0 character 1 character 2
372 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.6.2 basic operation 26.6.2.1 initialization the following registers are enable-protected, meaning t hat they can only be written when the spi is disabled (ctrl.enable is zero): z control a register (ctrla), except enable (c trla.enable) and software reset (ctrla.swrst) z control b register (ctrlb), except receiver enable (rxen) z baud register (baud) z address register (addr) any writes to these registers when the spi is enabled or is being enabled (ctrl.enable is one) will be discarded. writes to these registers while the spi is being disabled will be completed after the disabling is complete. enable-protection is denoted by the enable-prot ection property in the register description. before the spi is enabled, it must be configured, as outlined by the following steps: z spi mode in master or slave operation must be selected by writing 0x2 or 0x3 to the operating mode bit group in the control a register (ctrla.mode) z transfer mode must be selected by writing the clock polarity bit and the clock phase bit in the control a register (ctrla.cpol and ctrla.cpha) z transaction format must be selected by writing t he frame format bit group in the control a register (ctrla.form) z sercom pad to use for the receiver must be selected by writing the data in pinout bit in the control a register (ctrla.dipo) z sercom pads to use for the transmitter, slave select and serial clock must be selected by writing the data out pinout bit group in the control a register (ctrla.dopo) z character size must be selected by writing the characte r size bit in the control b register (ctrlb.chsize) z data direction must be selected by writing the data order bit in the control a register (ctrla.dord) z if the spi is used in master mode, the baud register (baud) must be written to generate the desired baud rate z the receiver can be enabled by writing a one to the receiv er enable bit in the control b register (ctrlb.rxen) 26.6.2.2 enabling, disabling and resetting the spi is enabled by writing a one to the enable bit in the control a register (ctrla.ena ble). the spi is disabled by writing a zero to ctrla.enable. the spi is reset by writing a one to the software reset bit in the control a register (ctrla.swrst). all registers in the spi, except dbgctrl, will be reset to their initial state, and the spi will be disabled. refer to ctrla for details. 26.6.2.3 clock generation in spi master operation (ctrla.mode is 0x3), the serial clock (sck) is generated internally using the sercom baud- rate generator. when used in spi mode, the baud-rate generator is set to synchronous mode, and the 8-bit baud register (baud) value is used to generate sck, clocking the shift register. refer to ?clock generation ? baud-rate generator? on page 340 for more details. in spi slave operation (ctrla.mode is 0x2), the clock is prov ided by an external master on the sck pin. this clock is used to directly clock the spi shift register. 26.6.2.4 data register the spi transmit data register (txdata) and spi receive data register (rxdata) share the same i/o address, referred to as the spi data register (data). writing the data register will update the transmit data register. reading the data register will return the contents of the receive data register. 26.6.2.5 spi transfer modes there are four combinations of sck phase and polarity with re spect to the serial data. the spi data transfer modes are shown in table 26-2 and figure 26-3 . sck phase is selected by the clock phase bit in the control a register
373 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 (ctrla.cpha). sck polarity is selected by the clock polarity bit in the control a register (ctrla.cpol). data bits are shifted out and latched in on opposite edges of the sck signal, ens uring sufficient time for the data signals to stabilize. table 26-2. spi transfer modes leading edge is the first clock edge in a clock cycle, while trailing edge is the second clock edge in a clock cycle. figure 26-3. spi transfer modes 26.6.2.6 transferring data master when configured as a master (ctrla.mode is 0x3), the _ss line can be located at any general purpose i/o pin, and must be configured as an output. when the spi is ready for a data transaction, software must pull the _ss line low. when writing a character to the data regi ster (data), the character will be transferre d to the shift register when the shift register is empty. once the contents of txdata have been trans ferred to the shift register, the data register empty flag in the interrupt flag status and clear register (intflag. dre) is set, and a new character can be written to data. as each character is shifted out from the master, another charac ter is shifted in from the slave. if the receiver is enabled (ctrla.rxen is one), the contents of the shift register will be transferred to the two-level receive buffer. the transfer takes place in the same clock cycle as the last data bit is shifted in, and the receive complete interrupt flag in the mode cpol cpha leading edge trailing edge 0 0 0 rising, sample falling, setup 1 0 1 rising, setup falling, sample 2 1 0 falling, sample rising, setup 3 1 1 falling, setup rising, sample -ode 3!-0,%) -/3)-)3/ #(!.'% -/3)0). #(!.'% -)3/0). -ode
374 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 interrupt flag status and clear register (intflag.rxc) will be set. the received data can be retrieved by reading data. when the last character has been transmitted and there is no va lid data in data, the transmit complete interrupt flag in the interrupt flag status and clear register (intflag.txc) is set. when the transaction is finished, the master must indicate this to the slave by pulling the _ss line high. slave when configured as a slave (ctrla.mode is 0x2), the spi inte rface will remain inactive, with the miso line tri-stated as long as the _ss pin is pulled high. software may update the contents of data at any time, as long as the data register empty flag in the interrupt status and clear register (intflag.dre) is set. when _ss is pulled low and sck is running, the slave will sample and shift out data according to the transaction mode set. when the contents of txdata have been loaded into the shift register, intflag.dre is set, and new data can be written to data. similar to the master, the slave will rece ive one character for each character transmitted. on the same clock cycle as the last data bit of a character is received, the character will be transferred into the two-level receive buffe r. the received character can be retrieved from data when intflag.rcx is set. when the master pulls the _ss line high, the transaction is done and the transmit complete interrupt flag in the interrupt flag status and clear register (txc) is set. once data is written, it takes three sck clocks to load the shi ft register. after the data register is empty, it takes three clk_sercom_apb cycles for intflag.dre to be set. 26.6.2.7 receiver error bit the spi receiver has one error bit: the buffer overflow bi t (bufovf), which can be read from the status register (status). upon error detection, the bit will be set until it is cleared by writing a one to it. the bit is also automatically cleared when the receiver is disabled. if the receive buffer is full and another character is received, this constitutes a buffer overflow condition (bufovf). when the full condition is no longer present, the overflow condition will be written to the receive buffer, along with the next fram e received. refer to status for further details. 26.6.3 additional features 26.6.3.1 address recognition when the spi is configured for slave operation (ctrla.mod e is 0x2) with address recognition (ctrla.form is 0x2), the sercom address recognition logic is enabled. when addr ess recognition is enabled, the first character in a transaction is checked for an address match. if there is a match, then the receive complete interrupt flag in the interrupt flag status and clear register (intflag.rxc) is set, the miso output is enabled and the transaction is processed. if there is no match, the transaction is ignored. if the device is in sleep mode, an address match can wake up the device in order to process the transaction. if the address does not match, then the complete transaction is ignored. if a 9-bit frame format is selected, only the lower 8 bits of the shift register are checked against the address register (addr). refer to ?address match and mask? on page 343 for further details. 26.6.3.2 preloading of the slave shift register when starting a transaction, the slave will first transmit the contents of the shift register before loading new data from data. the first character sent can be either the reset value of the shift register (if this is the first transmission since the last reset) or the last character in the previous transmission. preloading can be used to preload data to the shift register while _ss is high and eliminate sending a dummy character when starting a transaction. in order to guarantee enough set-up time before the first sck edge, enough time must be given between _ss going low and the first sck sampling edge, as shown in figure 26-4 . refer to for further details regarding the timing.
375 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 preloading is enabled by setting the slave data preload e nable bit in the control b register (ctrlb.ploaden). figure 26-4. timing using preloading only one data character written to data will be preloaded into the shift register while the synchronized _ss signal (see figure 26-4 ) is high. the next character written to data before _ss is pulled low will be stored in data until transfer begins. if the shift register is not preloaded, the current contents of the shift register will be shifted out. 26.6.3.3 master with several slaves if the bus consists of several spi slaves, an spi master c an use general purpose i/o pins to control the _ss line to each of the slaves on the bus, as shown in figure 26-5 . in this configuration, the single selected spi slave will drive the tri- state miso line. figure 26-5. multiple slaves in parallel an alternate configuration is shown in figure 26-6 . in this configuration, all n attached slaves are connected in series. a common _ss line is provided to all slaves, enabling them simultaneously. the master must shift n characters for a complete transaction. _ss synchronization to system domain miso to sck setup time required _ss to sck time using preloaden _ss synchronized to system domain sck shift register shift register mosi miso sck _ss [0] mosi miso _ss sck shift register mosi miso _ss sck spi master spi slave 0 _ss[n-1] spi slave n-1
376 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 26-6. multiple slaves in series 26.6.4 interrupts the spi has the following interrupt sources: z receive complete z transmit complete z data register empty each interrupt source has an interrupt flag associated with i t. the interrupt flag in the interrupt flag status and clear register (intflag) is set when the interrupt condition occu rs. each interrupt can be individually enabled by writing a one to the corresponding bit in the interrupt enable set regi ster (intenset), and disabled by writing a one to the corresponding bit in the interrupt enable clear register (int enclr). an interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the spi is reset. see t he register description for details on how to clear interrupt flag s. the spi has one common interrupt request line for all the interrupt sources. the user must read intflag to determine which interrupt condition is present. note that interrupts must be globally enabled for interrupt requests to be generated. refer to ?nested vector interrupt controller? on page 28 for details. for details on clearing interrupt flags, refer to intflag . 26.6.5 events not applicable. 26.6.6 sleep mode operation during master operation, the generic clock will continue to run in idle sleep mode. if the run in standby bit in the control a register (ctrla.r unstdby) is one, the gclk_sercom_core will also be enabled in standby sleep mode. any interrupt can wake up the device. if ctrla.runstdby is zero during master operation, glk_sercomx_core will be disabled when the ongoing transaction is finished. any interrupt can wake up the device. during slave operation, writing a one to ctrla.runstdby will allow the receive complete interrupt to wake up the device. if ctrla.runstdby is zero during sl ave operation, all reception will be dropped, including the ongoing transaction. shift register shift register mosi miso sck _ss mosi miso _ss sck shift register mosi miso _ss sck spi master spi slave 0 spi slave n-1
377 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.6.7 synchronization due to the asynchronicity between clk_sercomx_ap b and gclk_sercomx_core, some registers must be synchronized when accessed. a register can require: z synchronization when written z synchronization when read z synchronization when written and read z no synchronization when executing an operation that requires synchronization, the synchronization busy bit in the status register (status.syncbusy) will be set immediately, and cleared when synchronization is complete. if an operation that requires synchronization is executed wh ile status.syncbusy is one, the bus will be stalled. all operations will complete successfully, but the cpu will be stalled and interrupts will be pending as long as the bus is stalled. the following bits need synchronization when written: z software reset bit in the control a register (ctrla.swrst) z enable bit in the control a register (ctrla.enable) z receiver enable bit in the co ntrol b register (ctrlb.rxen) ctrlb.rxen behaves somewhat differently than described above. refer to ctrlb for details. write-synchronization is denoted by the write-synchronized property in the register description.
378 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.7 register summary offset name bit pos. 0x00 ctrla 7:0 runstdby mode[2:0] enable swrst 0x01 15:8 0x02 23:16 dipo[1:0] dopo 0x03 31:24 dord cpol cpha form[3:0] 0x04 ctrlb 7:0 ploaden chsize[2:0] 0x05 15:8 amode[1:0] 0x06 23:16 rxen 0x07 31:24 0x08 dbgctrl 7:0 dbgstop 0x09 reserved 0x0a baud 7:0 baud[7:0] 0x0b reserved 0x0c intenclr 7:0 rxc txc dre 0x0d intenset 7:0 rxc txc dre 0x0e intflag 7:0 rxc txc dre 0x0f reserved 0x10 status 7:0 bufovf 0x11 15:8 syncbusy 0x12 reserved 0x13 reserved 0x14 addr 7:0 addr[7:0] 0x15 15:8 0x16 23:16 addrmask[7:0] 0x17 31:24 0x18 data 7:0 data[7:0] 0x19 15:8 data[8] 0x1a reserved 0x1b reserved 0x1c reserved 0x1d reserved 0x1e reserved 0x1f reserved
379 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each individual register description. refer to ?register access protection? on page 371 for details. some registers require synchronization when read and/or written. write-synchronization is denoted by the write- synchronized property in each individual register description. refer to ?synchronization? on page 377 for details. some registers are enable-protected, meaning they can only be written when the usart is disabled. enable-protection is denoted by the enable-protected property in each individual register description.
380 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.8.1 control a name: ctrla offset: 0x00 reset: 0x00000000 property: write-protected, enable-protected, write-synchronized z bit 31 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 30 ? dord: data order this bit indicates the data order when a character is shifted out from the data register. 0: msb is transferred first. 1: lsb is transferred first. this bit is not synchronized. z bit 29 ? cpol: clock polarity in combination with the clock phase bit (cpha), this bit determines the spi transfer mode. 0: sck is low when idle. the leading edge of a clock cycle is a rising edge, while the trailing edge is a falling edge. 1: sck is high when idle. the leading edge of a clock cycle is a falling edge, while the trailing edge is a rising edge. this bit is not synchronized. z bit 28 ? cpha: clock phase in combination with the clock polarity bit (cpol), this bit determines the spi transfer mode. bit3130292827262524 dord cpol cpha form[3:0] access r r/w r/w r/w r/w r/w r/w r/w reset00000000 bit2322212019181716 dipo[1:0] dopo access r r r/w r/w r r r r/w reset00000000 bit151413121110 9 8 accessrrrrrrrr reset00000000 bit76543210 runstdby mode[2:0] enable swrst access r/w r r r/w r/w r/w r/w r/w reset00000000
381 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 0: the data is sampled on a leading sck edge and changed on a trailing sck edge. 1: the data is sampled on a trailing sck edge and changed on a leading sck edge. this bit is not synchronized. table 26-3. spi transfer modes z bits 27:24 ? form[3:0]: frame format table 26-4 shows the various frame formats supported by the sp i. when a frame format with address is selected, the first byte received is checked against the addr register. table 26-4. frame format z bits 23:22 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 21:20 ? dipo[1:0]: data in pinout these bits define the data in (di) pad configurations. in master operation, di is miso. in slave operation, di is mosi. these bits are not synchronized. table 26-5. receive data pinout z bits 19:17 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. mode cpol cpha leading edge trailing edge 0x0 0 0 rising, sample falling, change 0x1 0 1 rising, change falling, sample 0x2 1 0 falling, sample rising, change 0x3 1 1 falling, change rising, sample form[3:0] name description 0x0 spi spi frame 0x1 - reserved 0x2 spi_addr spi frame with address 0x3-0xf - reserved dipo[1:0] name description 0x0 pad0 sercom_pad0 as data in 0x1 pad1 sercom_pad1 as data in 0x2 pad2 sercom_pad2 as data in 0x3 pad3 sercom_pad3 as data in
382 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bit 16 ? dopo: data out pinout this bit defines the available pad configurations for data out (do) and the serial clock (sck). in slave operation, the slave select line (_ss) is controlled by dopo, while in master operation the _ss line is controlled by the port configuration. in master operation, do is mosi. in slave operation, do is miso. this bit is not synchronized. table 26-6. data out pinout z bits 15:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 7 ? runstdby: run in standby this bit defines the functionality in standby sleep mode. these bits are not synchronized. table 26-7. run in standby configuration z bits 6:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 4:2 ? mode: operating mode these bits must be written to 0x2 or 0x3 to select the spi serial communication interface of the sercom. 0x2: spi slave operation 0x3: spi master operation these bits are not synchronized. z bit 1 ? enable: enable 0: the peripheral is disabled or being disabled. 1: the peripheral is enabled or being enabled. due to synchronization, there is delay from writing ctrla.enable until the peripheral is enabled/disabled. the value written to ctrl.enable will read back immediately and the synchronization busy bit in the status register (status.syncbusy) will be set. status.syncbus y is cleared when the operation is complete. this bit is not enable-protected. z bit 0 ? swrst: software reset 0: there is no reset operation ongoing. 1: the reset operation is ongoing. dopo do sck slave _ss master _ss 0x0 sercom_pad0 sercom_pad1 sercom_pad2 system configuration 0x1 sercom_pad2 sercom_pad3 sercom_pad1 system configuration runstdby slave master 0x0 disabled. all reception is dropped, including the ongoing transaction. genericclock is disabled when ongoing transaction is finished. all interrupts can wake up the device. 0x1 wake on receive complete interrupt. genericclock is enabled while in sleep modes. all interrupts can wake up the device.
383 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 writing a zero to this bit has no effect. writing a one to this bit resets all registers in the serc om, except dbgctrl, to their initial state, and the ser- com will be disabled. writing a one to ctrl.swrst will always take precedence, meaning that all other writes in the same write-oper- ation will be discarded. due to synchronization, there is a delay from writing ctrla.swrst until the reset is complete. ctrla.swrst and status.syncbusy will both be cl eared when the reset is complete. this bit is not enable-protected.
384 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.8.2 control b name: ctrlb offset: 0x04 reset: 0x00000000 property: write-protected, enable-protected z bits 31:18 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 17 ? rxen: receiver enable 0: the receiver is disabled or being enabled. 1: the receiver is enabled or it will be enabled when spi is enabled. writing a zero to this bit will disable the spi receiver immediately. the receive buffer will be flushed, data from ongoing receptions will be lost and status.bufovf will be cleared. writing a one to ctrlb.rxen when the spi is disabl ed will set ctrlb.rxen immediately. when the spi is enabled, ctrlb.rxen will be cleared, status.syncbusy will be set and remain set until the receiver is enabled. when the receiver is enabled ctrlb.rxen will read back as one. writing a one to ctrlb.rxen when the spi is enabled will se t status.syncbusy, which will remain set until the receiver is enabled, and ctrlb.rxen will read back as one. this bit is not enable-protected. z bit 16 ? reserved bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 rxen accessr/wr/wr/wrrrrr reset00000000 bit151413121110 9 8 amode[1:0] accessr/wr/wrrrrrr reset00000000 bit76543210 ploaden chsize[2:0] access r r/w r r r r/w r/w r/w reset00000000
385 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 15:14 ? amode: address mode these bits set the slave addressing mode when the frame format (ctrla.form) with address is used. they are unused in master mode. table 26-8. address mode z bits 13:7 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 6 ? ploaden: slave data preload enable setting this bit will enable preloading of the slave shift register when there is no transfer in progress. if the _ss line is high when data is written, it will be tr ansferred immediately to the shift register. z bits 5:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 2:0 ? chsize[2:0]: character size table 26-9. character size amode[1:0] name description 0x0 mask addrmask is used as a mask to the addr register 0x1 2_addrs the slave responds to the two unique addresses in addr and addrmask 0x2 range the slave responds to the range of addresses between and including addr and addrmask. addr is the upper limit 0x3 reserved chsize[2:0] name description 0x0 8bit 8 bits 0x1 9bit 9 bits 0x2-0x7 reserved
386 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.8.3 debug control name: dbgctrl offset: 0x08 reset: 0x00 property: write-protected z bits 7:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? dbgstop: debug stop mode this bit controls the functionality when the cpu is halted by an external debugger. 0: the baud-rate generator continues normal operati on when the cpu is halted by an external debugger. 1: the baud-rate generator is halted when the cpu is halted by an external debugger. bit76543210 dbgstop accessrrrrrrrr/w reset00000000
387 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.8.4 baud rate name: baud offset: 0x0a reset: 0x00 property: write-protected, enable-protected z bits 7:0 ? baud: baud register these bits control the clock generation, as described in the sercom ?clock generation ? baud-rate generator? on page 340 . bit76543210 baud[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
388 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.8.5 interrupt enable clear this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable set register (intenset) . name: intenclr offset: 0x0c reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? rxc: receive comp lete interrupt enable 0: receive complete interrupt is disabled. 1: receive complete interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the receive complete in terrupt enable bit, which disables the receive complete interrupt. z bit 1 ? txc: transmit co mplete interrupt enable 0: transmit complete interrupt is disabled. 1: transmit complete interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the transmit complete interrupt enable bit, which disable the transmit complete interrupt. z bit 0 ? dre: data register empty interrupt enable 0: data register empty interrupt is disabled. 1: data register empty interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the data register empty interrupt enable bit, which disables the data register empty interrupt. bit76543210 rxc txc dre accessrrrrrr/wr/wr/w reset00000000
389 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.8.6 interrupt enable set this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear register (intenclr) . name: intenset offset: 0x0d reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? rxc: receive comp lete interrupt enable 0: receive complete interrupt is disabled. 1: receive complete interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the receive complete interrupt enable bit, which enables the receive complete interrupt. z bit 1 ? txc: transmit co mplete interrupt enable 0: transmit complete interrupt is disabled. 1: transmit complete interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the transmit complete interrupt enable bit, which enables the transmit complete interrupt. z bit 0 ? dre: data register empty interrupt enable 0: data register empty interrupt is disabled. 1: data register empty interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the data register empty interrupt enable bit, which enables the data register empty interrupt. bit76543210 rxc txc dre accessrrrrrr/wr/wr/w reset00000000
390 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.8.7 interrupt flag status and clear name: intflag offset: 0x0e reset: 0x00 property: - z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? rxc: receive complete this flag is cleared by reading the data (data) register or by disabling the receiver. this flag is set when there are unread data in the receive buffer. if address matching is enabled, the first data received in a transaction will be an address. writing a zero to this bit has no effect. writing a one to this bit has no effect. z bit 1 ? txc: transmit complete this flag is cleared by writing a one to it or by writing new data to data. in master mode, this flag is set when the data have been shifted out and there are no new data in data. in slave mode, this flag is set when the _ss pin is pulled high. if address matching is enabled, this flag is only set if the transaction was initiated with an address match. writing a zero to this bit has no effect. writing a one to this bit will clear the flag. z bit 0 ? dre: data register empty this flag is cleared by writing new data to data. this flag is set when data is empty and ready for new data to transmit. writing a zero to this bit has no effect. writing a one to this bit has no effect. bit76543210 rxc txc dre accessrrrrrrr/wr reset00000000
391 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.8.8 status name: status offset: 0x10 reset: 0x0000 property: ? z bit 15 ? syncbusy: synchronization busy this bit is cleared when the synchronization of registers between the clock domains is complete. this bit is set when the synchronization of registers between clock domains is in progress. z bits 14:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? bufovf: buffer overflow reading this bit before reading data will indicate the error status of the next character to be read. this bit is cleared by writing a one to the bit or by disabling the receiver. this bit is set when the first character received after an overflow condition has been eliminated is available in rxdata. an overflow condition occurs if the two-level rece ive buffer is full when the last bit of the incoming char- acter is shifted into the shift register. all characters shif ted into the shift registers before the overflow condition is eliminated by reading data will be lost. writing a zero to this bit has no effect. writing a one to this bit will clear it. z bits 1:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. bit151413121110 9 8 syncbusy accessrrrrrrrr reset00000000 bit76543210 bufovf accessrrrrrr/wrr reset00000000
392 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.8.9 address name: addr offset: 0x14 reset: 0x00000000 property: write-protected, enable-protected z bits 31:24 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 23:16 ? addrmask[7:0]: address mask these bits hold the address mask when the transacti on format (ctrla.form) with address is used. z bits 15:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 7:0 ? addr[7:0]: address these bits hold the address when the transacti on format (ctrla.form) with address is used. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 addrmask[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit151413121110 9 8 accessrrrrrrrr reset00000000 bit76543210 addr[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
393 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 26.8.10 data name: data offset: 0x18 reset: 0x0000 property: ? z bits 15:9 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 8:0 ? data[8:0]: data reading these bits will return the contents of the receive data buffer. the register should be read only when the receive complete interrupt flag bit in the interrupt flag status and clear register (intflag.rxcif) is set. writing these bits will write the transmit data buffer. th is register should be written only when the data register empty interrupt flag bit in the interrupt flag st atus and clear register (intflag.dreif) is set. bit151413121110 9 8 data[8] accessrrrrrrrr/w reset00000000 bit76543210 data[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
394 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27. sercom i 2 c ? sercom inter-integrated circuit 27.1 overview the inter-integrated circuit (i 2 c) interface is one of the available modes in the serial communication interface (sercom). refer to ?sercom ? serial communication interface? on page 337 for details. the i 2 c interface uses the sercom transmitter and receiver configured as shown in figure 27-1 . fields shown in capital letters are registers accessible by the cpu, while lowercase fields are internal to the sercom. each side, master and slave, depicts a separate i 2 c interface containing a shift register, a transmit buffer and a receive buffer. in addition, the i 2 c master uses the sercom baud-rate generator, while the i 2 c slave uses the sercom address match logic. 27.2 features z master or slave operation z philips i 2 c compatible z smbus ? compatible z 100khz and 400khz support at low system clock frequencies z physical interface includes: z slew-rate limited outputs z filtered inputs z slave operation: z operation in all sleep modes z wake-up on address match z address match in hardware for: z 7-bit unique address and/or 7-bit general call address z 7-bit address range z two unique 7-bit addresses 27.3 block diagram figure 27-1. i 2 c single-master single-slave interconnection shift register shift register master slave sda scl tx data rx data tx data rx data == addr/addrmask baud baud rate generator scl low hold 0 0 0 0
395 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.4 signal description refer to ?i/o multiplexing and considerations? on page 15 for details on the pin mapping for this peripheral. one signal can be mapped on several pins. note that not all the pins are i 2 c pins. refer to table 6-1 for details on the pin type for each pin, and for details on the elec trical characteristics of the different pin types. 27.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 27.5.1 i/o lines using the sercom?s i/o lines requires the i/o pins to be configured. refer to ?port? on page 289 for details. 27.5.2 power management the i 2 c will continue to operate in any sleep mode where the selected source clock is running. i 2 c interrupts can be used to wake up the device from sleep modes. the events can trigger other operations in the system without exiting sleep modes. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. 27.5.3 clocks the sercom bus clock (clk_sercomi_apb, where i repr esents the specific sercom instance number) is enabled by default, and can be enabled and disabled in the power manager. refer to ?pm ? power manager? on page 105 for details. the sercom bus clock (clk_serco mi_apb) is enabled by default, and can be enabled and disabled in the power manager. refer to ?pm ? power manager? on page 105 for details. two generic clocks are used by the sercom (gclk_sercomi_core and gclk_sercom_slow). the core clock (gclk_sercomi_core) is required to clock the sercom while operating as a master, while the slow clock (gclk_sercom_slow) is required only for certain functions. these clocks must be configured and enabled in the generic clock controller (gclk) before using the sercom. refer to ?gclk ? generic clock controller? on page 83 for details. these generic clocks are asynchronous to the sercom bus clock (clk_sercomi_apb). due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. refer to the ?synchronization? on page 407 section for further details. 27.5.4 dma not applicable. 27.5.5 interrupts the interrupt request line is connected to the interrupt controller. using the i 2 c interrupts requires the interrupt controller to be configured first. refer to ?nested vector interrupt controller? on page 28 for details. 27.5.6 events not applicable. signal name type description pad[0] digital i/o sda pad[1] digital i/o scl pad[2] digital i/o sda_out (4-wire) pad[3] digital i/o sdc_out (4-wire)
396 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.5.7 debug operation when the cpu is halted in debug mode, the i 2 c interface continues normal operation. if the i 2 c interface is configured in a way that requires it to be periodically serviced by the cp u through interrupts or similar, improper operation or data loss may result during debugging. the i 2 c interface can be forced to halt operation during debugging. refer to the dbgctrl register for details. 27.5.8 register access protection all registers with write-access are optionally write-protected by the peripheral access controller (pac), except the following registers: z interrupt flag status and clear register (intflag) z status register (status) z address register (addr) z data register (data) write-protection is denoted by the write-protected property in the register description. write-protection does not apply to accesses through en external debugger. refer to ?pac ? peripheral access controller? on page 31 for details. 27.5.9 analog connections not applicable. 27.6 functional description 27.6.1 principle of operation the i 2 c interface uses two physical lines for communication: z serial data line (sda) for packet transfer z serial clock line (scl) for the bus clock a transaction starts with the start condition, followed by a 7-bit address and a direction bit (read or write) sent from the i 2 c master. the addressed i 2 c slave will then acknowledge (ack) the address, and data packet transactions can commence. every 9-bit data packet consists of 8 data bits followed by a one-bit reply indicating whether the data was acknowledged or not. in the eventthat a data packet is not acknowledged (nack), whether sent from the i 2 c slave or master, it will be up to the i 2 c master to either terminate the connection by issuing the stop condition, or send a repeated start if more data is to be tranceived. figure 27-2 illustrates the possible transaction formats and figure 27-3 explains the legend used.
397 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 27-2. basic i 2 c transaction diagram figure 27-3. transaction diagram syntax 27.6.2 basic operation 27.6.2.1 initialization the following registers are enable-protected, meaning they can be written only when the i 2 c interface is disabled (ctrla.enable is zero): z control a register (ctrla), except enable (c trla.enable) and software reset (ctrla.swrst) z control b register (ctrlb), except acknowl edge action (ctrlb.ackact) and command (ctrlb.cmd) z baud rate register (baud) z address register (addr) while in slave operation p s address 6 ... 0 r/w ack ack 7 ... 0 data ack/nack 7 ... 0 data sda scl s a a/a r/w address data p a data address packet data packet #0 transaction data packet #1 direction "0" "1" master drives bus slave drives bus either master or slave drives bus s sr p start condition repeated start condition stop condition a a acknowledge (ack) not acknowledge (nack) r w master read master write data packet direction: "0" "1" acknowledge: bus driver: special bus conditions
398 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 any writes to these bits or registers when the i 2 c interface is enabled or is being enabled (ctrla.enable is one) will be discarded. writes to these registers while the i 2 c interface is being disabled will be completed after the disabling is complete. enable-protection is denoted by the enable-prot ection property in the register description. before the i 2 c interface is enabled, it must be configured as outlined by the following steps: i 2 c mode in master or slave operation must be selected by wr iting 0x4 or 0x5 to the operating mode bit group in the control a register (ctrla.mode) z scl low time-out can be enabled by writing to the scl low time-out bit in the control a register (ctrla.lowtout) z in master operation, the inactive bus time-out can be set in the inactive time-out bit group in the control a register (ctrla.inactout) z hold time for sda can be set in the sda hold time bit group in the control a register (ctrla.sdahold) z smart operation can be enabled by writing to the sm art mode enable bit in the control b register (ctrlb.smen) z in slave operation, the address match configuration must be set in the address mode bit group in the control b register (ctrlb.amode) z in slave operation, the addresses must be set, according to the selected address configuration, in the address and address mask bit groups in the addr ess register (addr.addr and addr.addrmask) z in master operation, the baud rate register (bau d) must be written to generate the desired baud rate 27.6.2.2 enabling, disabling and resetting the i 2 c interface is enabled by writing a one to the enable bit in the control a register (ctrla.enable). the i 2 c interface is disabled by writing a zero to ctrla.enable. the i 2 c interface is reset by writing a one to the software reset bit in the control a register (ctrla.swrst). all registers in the i 2 c interface, except dbgctrl, will be reset to their initial state, and the i 2 c interface will be disabled. refer to ctrla for details. 27.6.2.3 i 2 c bus state logic the bus state logic includes several logic blocks that continuously monitor the activity on the i 2 c bus lines in all sleep modes. the start and stop detectors and the bit counter are all essential in the process of determining the current bus state. the bus state is determined according to the state diagram shown in figure 27-4 . software can get the current bus state by reading the master bus state bits in the status register (status.busstate). the value of status.busstate in the figure is shown in binary.
399 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 27-4. bus state diagram the bus state machine is active when the i 2 c master is enabled. after the i 2 c master has been enabled, the bus state is unknown. from the unknown state, the bus state machine can be forced to enter the idle state by writing to status.busstate accordingly. however, if no action is tak en by software, the bus state will become idle if a stop condition is detected on the bus. if the inactive bus time-out is enabled, the bus state will change from unknown to idle on the occurrence of a time-out. note that after a known bus stat e is established, the bus state logic will not re-enter the unknwon state from either of the other states. when the bus is idle it is ready for a new transaction . if a start condition is issued on the bus by another i 2 c master in a multimaster setup, the bus becomes busy until a stop condition is detected. the stop condition will cause the bus to re- enter the idle state. if the inactive bus time-out (smbus) is enabled, the bus state will change from busy to idle on the occurrence of a time-out. if a start condition is generated in ternally by writing the address bit group in the address register (addr.addr) while in idle state, the owner stat e is entered. if the complete transaction was performed without interference, i.e., arbitration not lost, the i 2 c master is allowed to issue a stop condition, which in turn will cause a change of the bus state back to idle. however, if a packet collision is detected, the arbitration is assumed lost and the bus state becomes busy until a stop condition is detected. a repeated start condition will change the bus state only if arbitration is lost while issuing a repeated start. 27.6.2.4 clock generation the master i 2 c clock (scl) frequency is determined by a number of factors. the low (t low ) and high (t _high ) times are determined by the baud rate register (baud), while the rise (t rise ) and fall (t fall ) times are determined by the bus topology. because of the wired-and logic of the bus, t fall will be considered as part of t low . likewise, t rise will be in a state between t low and t high until a high state has been detected. p + timeout reset wri te addr (s) idle (0b01) s busy (0b11) p + ti meout unknown (0b00) owner (0b10) arbitration lost command p wr i t e addr (sr ) sr
400 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 27-5. scl timing the following parameters are timed using the scl low time per iod. this comes from the master baud rate low bit group in the baud rate register (baud.ba udlow) when non-zero, or the master baud rate bit group in the baud rate register (baud.baud) when baud.baudlow is zero. z t low ? low period of scl clock z t su;sto ? set-up time for stop condition z t buf ? bus free time between stop and start conditions z t hd;sta ? hold time (repeated) start condition z t su;sta ? set-up time for repeated start condition z t high is timed using the scl high time count from baud.baud z t rise is determined by the bus impedance; for internal pull-ups see electrical characteristics z t fall is determined by the open-drain current limit and bus impedance; can typically be regarded as zero; see electrical characteristics the scl frequency is given by: when baud.baudlow is zero, the baud.b aud value is used to time both scl high and scl low. in this case the following formula will give the scl frequency: when baud.baudlow is non-zero, the following formula is used to determine the scl frequency: t hd;sta t low t high t buf t rise scl sda t su;sto t su;sta ps sr t fall rise high low scl t t t f + + = 1 rise gclk gclk scl t baud f f f + + = ) 5 ( 2 rise gclk gclk scl t baudlow baud f f f + + + = 10
401 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 when baudlow is non-zero, the following formula can be used to determine the scl frequency: the following formulas can be used to determine the scl t low and t high times: 27.6.2.5 i 2 c master operation the i 2 c master is byte-oriented and interrupt based. the number of interrupts generated is kept at a minimum by automatic handling of most events. auto-triggering of operations and a special smart mode, which can be enabled by writing a one to the smart mode enable bit in the control a register (ctrla.smen), are included to reduce software driver complexity and code size. the i 2 c master operates according to the behavior diagram shown in figure 27-6 . the circles with a capital em followed by a number (m1, m2... etc.) indicate which node in the figure the bus logic can jump to based on software or hardware interaction. this diagram is used as reference for the description of the i 2 c master operation throughout the document. rise gclk gclk scl t baudlow baud f f f + + + = 10 gclk low f baudlow baud t 5 . + = gclk high f baud baud t 5 . + =
402 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 27-6. i 2 c master behavioral diagram transmitting address packets the i 2 c master starts a bus transaction by writing addr.addr with the i 2 c slave address and the direction bit. if the bus is busy, the i 2 c master will wait until the bus becomes idle before continuing the operation. when the bus is idle, the i 2 c master will issue a start condition on the bus. the i 2 c master will then transmit an address packet using the address written to addr.addr. after the address packet has been transmitted by the i 2 c master, one of four cases will arise, based on arbitration and transfer direction. case 1: arbitration lost or bus error during address packet transmission if arbitration was lost during transmission of the address packet, the master on bus bit in the interrupt flag register (intflag.mb) and the arbitration lost bit in the status regi ster (status.arblost) are both set. serial data output to sda is disabled, and the scl is released, which disables clock stretching. in effect ,the i 2 c master is no longer allowed to perform any operation on the bus until the bus is idle again. a bus error will behave similarly to the arbitration lost condition. in this case, the mb interrupt flag and master bus error bit in the status regi ster (status.buserr) are both set in addition to status.arblost. the master received not acknowledge bit in the status register (status.rxnack) will always contain the last successfully received acknowledge or not acknowledge indication. in this case, software will typically inform the application code of the condition and then clear the interrupt flag before exiting the interrupt routine. no other flags have to be clea red at this point, because all flags will be cleared automatically the next time the addr.addr register is written. case 2: address packet transmit complete ? no ack received if no i 2 c slave device responds to the address packet, then t he intflag.mb interrupt flag is set and status.rxnack is set. the clock hold is active at this point, preventing further activity on the bus. idle s busy busy p sr p m3 m3 m2 m2 m1 m1 r data address w a/a data wait for idle application s w s w sr p m3 m2 busy m4 a s w a/a a/a a/a m4 a idle idle master read interrupt + hold master write interrupt + hold s w s w s w busy r/w s w software interaction the master provides data on the bus addressed slave provides data on the bus a a r/w busy m4
403 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 the missing ack response can indicate that the i 2 c slave is busy with other tasks or sleeping and, therefore, not able to respond. in this event, the next step can be either issuing a stop condition (recommended) or resending the address packet by using a repeated start condition. however, the reason for the missing acknowledge can be that an invalid i 2 c slave address has been used or that the i 2 c slave is for some reason disconnected or faulty. if using smbus logic, the slave must ack the address, and hence no action means the slave is not available on the bus. case 3: address packet transmit comple te ? write packet, master on bus set if the i 2 c master receives an acknowledge response from the i 2 c slave, intflag.mb is set and status.rxnack is cleared. the clock hold is active at this point, preventing further activity on the bus. in this case, the software implementation becomes highl y protocol dependent. three possible actions can enable the i 2 c operation to continue. the three options are: z the data transmit operation is initiated by writing the data byte to be transmitted into data.data. z transmit a new address packet by writing addr.addr. a repeated start condition will automatically be inserted before the address packet. z issue a stop condition, consequently terminating the transaction. case 4: address packet transmit comp lete ? read packet, slave on bus set if the i 2 c master receives an ack from the i 2 c slave, the i 2 c master proceeds to receive the next byte of data from the i 2 c slave. when the first data byte is received, the slave on bus bit in the interrupt flag register (intflag.sb) is set and status.rxnack is cleared. the clo ck hold is active at this point, preventing further activity on the bus. in this case, the software implementation becomes highl y protocol dependent. three possible actions can enable the i 2 c operation to continue. the three options are: z let the i 2 c master continue to read data by first acknowledging the data received. this is automatically done when reading data.data if the smart mode is enabled. z transmit a new address packet. z terminate the transaction by issuing a stop condition. an ack or nack will be automatically transmitted for t he last two alternatives if smart mode is enabled. the acknowledge action bit in the control b register (ctrlb.a ckact) determines whether ac k or nack should be sent. transmitting data packets when an address packet with direction set to write (status.dir is zero) has been successfully transmitted, intflag.mb will be set and the i 2 c master can start transmitting data by writing to data.data. the i 2 c master transmits data via the i 2 c bus while continuously monitoring for packet collisions. if a collision is detected, the i 2 c master looses arbitration and stat us.arblost is set. if the transmit was successful, the i 2 c master automatically receives an ack bit from the i 2 c slave and status.rxnack will be cl eared. intflag.mb will be set in both cases, regardless of arbitration outcome. testing status.arblost and handling the arbitration lost condition in the beginning of the i 2 c master on bus interrupt is recommended. this can be done, as there is no differ ence between handling address and data packet arbitration. status.rxnack must be checked for each data packet transmitted before the next data packet transmission can commence. the i 2 c master is not allowed to continue transmitting data packets if a nack is given from the i 2 c slave. receiving data packets when intflag.sb is set, the i 2 c master will already have received one data packet. the i 2 c master must respond by sending either an ack or nack. sending a nack might not be successfully executed,as arbitration can be lost during the transmission. in this case, a loss of arbitration will cause intflag.sb to not be set on completion. instead, intflag.mb will be used to indicate a change in arbitration. h andling of lost arbitration is the same as for data bit transmission. 27.6.2.6 i 2 c slave operation the i 2 c slave is byte-oriented and interrupt-based. the number of interrupts generated is kept at a minimum by automatic handling of most events. auto triggering of oper ations and a special smart mode, which can be enabled by
404 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 writing a 1 to the smart mode enable bit in the control a register (ctrla.smen), are included to reduce software?s complexity and code size. the i 2 c slave operates according to the behavior diagram shown in figure 27-7 . the circles with a capital ess followed by a number (s1, s2... etc.) indicate which node in the fi gure the bus logic can jump to based on software or hardware interaction. this diagram is used as reference for the description of the i 2 c slave operation throughout the document. figure 27-7. i 2 c slave behavioral diagram receiving address packets when the i 2 c slave is properly configured, it will wait for a start condition to be detected. when a start condition is detected, the successive address packet will be received and checked by the address match logic. if the received address is not a match, the packet is rejected and the i 2 c slave waits for a new start condition. the i 2 c slave address match bit in the interrupt flag register (intflag.amatch) is set when a start condition followed by a valid address packet is detected. scl will be stretched until the i 2 c slave clears intflag.amatch. because the i 2 c slave holds the clock by forcing scl low, the software is given unlimited time to respond to the address. the direction of a transaction is determined by reading the read / write direction bit in the status register (status.dir), and the bit will be updated only when a valid address packet is received. if the transmit collision bit in the status register (status.coll) is set, this indicates that the last packet addressed to the i 2 c slave had a packet collision. a collision causes the sda and scl lines to be released without any notification to software. the next amatch interrupt is, therefore, the first indication of the previous packet?s collision. collisionsare intended to follow the smbus address resolution protocol (arp). after the address packet has been received from the i 2 c master, one of two cases will arise based on transfer direction. case 1: address packet accepted ? read flag set the status.dir bit is one, indicating an i 2 c master read operation. the scl line is forced low, stretching the bus clock. if an ack is sent, i 2 c slave hardware will set the data ready bit in the interrupt flag register (intflag.drdy), s s3 address s2 a s1 r w data a/a data p s2 sr s3 p s2 sr s3 slave address interrupt slave data interrupt a s w s w s w s w a/a a/a a s1 s w interrupt on stop condition enabled s1 slave stop interrupt s w software interaction the master provides data on the bus addressed slave provides data on the bus
405 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 indicating data are needed for transmit. if not acknowledge is sent, the i 2 c slave will wait for a new start condition and address match. typically, software will immediately acknowledge t he address packet by sending an ack/nack bit. the i 2 c slave command ctrlb.cmd = 3 can be used for both read and write operation,as the command execution is dependent on the status.dir bit. writing a one to intflag.amatch will also cause an ack/ nack to be sent corresponding to the ctrlb.ackact bit. case 2: address packet accepted ? write flag set the status.dir bit is cleared, indicating an i 2 c master write operation. the scl line is forced low, stretching the bus clock. if an ack is sent, the i 2 c slave will wait for data to be received. data, repeated start or stop can be received. if not acknowledge is sent, the i 2 c slave will wait for a new start condition and address match. typically, software will immediately acknowledge t he address packet by sending an ack/nack bit. the i 2 c slave command ctrlb.cmd = 3 can be used for both read and write operation,as the command execution is dependent on status.dir. writing a one to intflag.amatch will also cause an ack/ nack to be sent corresponding to the ctrlb.ackact bit. receiving and transmitting data packets after the i 2 c slave has received an address packet, it will respond according to the direction either by waiting for the data packet to be received or by startingto send a data packet by writing to data.data. when a data packet is received or sent, intflag.drdy will be set. then, if the i 2 c slave was receiving data, it will send an acknowledge according to ctrlb.ackact. case 1: data received intflag.drdy is set, and scl is held low pending sw interaction. case 2: data sent when a byte transmission is successfully completed, the intfla g.drdy interrupt flag is set. if nack is received, the i 2 c slave must expect a stop or a repeated start to be received. the i 2 c slave must release the data line to allow the i 2 c master to generate a stop or repeated start. upon stop detection, the stop received bit in the interrupt flag register (intflag.prec) will be set and the i 2 c slave will return to theidle state. 27.6.3 additional features 27.6.3.1 smbus the i 2 c hardware incorporates hardware scl low time-out, which allows a time-out to occur if the clock line is held low too long. this time-out is driven by the gclk_sercom_slow clock. the i 2 c interface also allows for a smbus compatible sda hold time. 27.6.3.2 smart mode the i 2 c interface incorporates a special smart mode that simplifies application code and minimizes the user interaction needed to keep hold of the i 2 c protocol. the smart mode accomplishes this by letting the reading of data.data automatically issue an ack or nack based on the state of ctrlb.ackact. 27.6.3.3 4-wire mode setting the pin usage bit in the control a register (ctrla .pinout) for master or slave to 4-wire mode enables operation as shown in figure 27-8 . in this mode, the internal i 2 c tri-state drivers are bypassed, and an external, i 2 c - compliant tri-state driver is needed when connecting to an i 2 c bus.
406 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 27-8. i2c pad interface 27.6.3.4 quick command setting the quick command enable bit in the control b register (ctrlb.qcen) enables quick command. when quick command is enabled, the corresponding interrupt flag is set immediately after the slave acknowledges the address. at this point, the software can either issue a stop command or a repeated start by writi ng ctrlb.cmd or addr.addr. 27.6.4 interrupts the i 2 c slave has the following interrupt sources: z data ready z address match z stop received the i 2 c master has the following interrupt sources: z slave on bus z master on bus each interrupt source has an interrupt flag associated with i t. the interrupt flag in the interrupt flag status and clear register (intflag) is set when the interrupt condition occu rs. each interrupt can be individually enabled by writing a one to the corresponding bit in the interrupt enable set regi ster (intenset), and disabled by writing a one to the corresponding bit in the interrupt enable clear register (int enclr). an interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the i 2 c is reset. see intflag for details on how to clear interrupt flags. the i 2 c has one common interrupt request line for all the interrupt sources. the user must read intflag to determine which interrupt condition is present. note that interrupts must be globally enabled for interrupt requests to be generated. refer to ?nested vector interrupt controller? on page 28 for details. 27.6.5 sleep mode operation during i 2 c master operation, the generic clock (gclk_sercomi_core) will continue to run in idle sleep mode. if the run in standby bit in the control a register (ctrla.runst dby) is one, the glk_sercomi_core will also run in standby sleep mode. any interrupt can wake up the device. if ctrla.runstdby is zero during i 2 c master operation, the glk_sercomi_core will be disabled when an ongoing transaction is finished. any interrupt can wake up the device. during i 2 c slave operation, writing a one to ctrla.runstdby will allow the address match interrupt to wake up the device. in i 2 c slave operation, all receptions will be dropped when ctrla.runstdby is zero. scl/sda pad i2c driver scl_out/ sda_out pad pinout scl_in/sda_in scl_out/sda_out pinout
407 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.6.6 synchronization due to the asynchronicity between clk_sercomi_ap b and gclk_sercomi_core, some registers must be synchronized when accessed. a register can require: z synchronization when written z synchronization when read z synchronization when written and read z no synchronization when executing an operation that requires synchronization, the synchronization busy bit in the status register (status.syncbusy) will be set immediately, and cleared when synchronization is complete. if an operation that requires synchronization is executed wh ile status.syncbusy is one, the bus will be stalled. all operations will complete successfully, but the cpu will be stalled and interrupts will be pending as long as the bus is stalled. the following register needs synchronization when written: z data (data) when in smart mode the following bits need synchronization when written: z software reset bit in the control a register (ctrla.swrst) z enable bit in the control a register (ctrla.enable) z write to bus state bits in the status register (status.busstate) z address bits in the address register (addr.addr) when in master operation write-synchronization is denoted by the write-synchronized property in the register description. the following register needs synchronization when read: z data (data) when in smart mode read-synchronization is denoted by the read-synchronized property in the register description.
408 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.7 register summary table 27-1. register summary ? slave mode offset name bit pos. 0x00 ctrla 7:0 runstdby mode[2:0]=100 enable swrst 0x01 15:8 0x02 23:16 sdahold[1:0] pinout 0x03 31:24 lowtout 0x04 ctrlb 7:0 0x05 15:8 amode[1:0] smen 0x06 23:16 ackact cmd[1:0] 0x07 31:24 0x08 reserved ... reserved 0x0b reserved 0x0c intenclr 7:0 drdy amatch prec 0x0d intenset 7:0 drdy amatch prec 0x0e intflag 7:0 drdy amatch prec 0x0f reserved
409 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 0x10 status 7:0 clkhold lowtout sr dir rxnack coll buserr 0x11 15:8 syncbusy 0x12 reserved 0x13 reserved 0x14 addr 7:0 addr[6:0] gencen 0x15 15:8 0x16 23:16 addrmask[6:0] 0x17 31:24 0x18 data 7:0 data[7:0] 0x19 15:8 table 27-1. register summary ? slave mode (continued) offset name bit pos.
410 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 27-2. register summary ? master mode offset name bit pos 0x00 ctrla 7:0 runstdby mode[2:0]=101 enable swrst 0x01 15:8 0x02 23:16 sdahold[1:0] pinout 0x03 31:24 lowtout inactout[1:0] 0x04 ctrlb 7:0 0x05 15:8 qcen smen 0x06 23:16 ackact cmd[1:0] 0x07 31:24 0x08 dbgctrl 7:0 dbgstop 0x09 reserved 0x0a baud 7:0 baud[7:0] 0x0b 15:8 baudlow[7:0] 0x0c intenclr 7:0 sb mb 0x0d intenset 7:0 sb mb 0x0e intflag 7:0 sb mb 0x0f reserved
411 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 0x10 status 7:0 clkhold lowtout busstate[1:0] rxnack arblost buserr 0x11 15:8 syncbusy 0x12 reserved 0x13 reserved 0x14 addr 7:0 addr[7:0] 0x15 15:8 0x16 reserved 0x17 reserved 0x18 data 7:0 data[7:0] 0x19 15:8 table 27-2. register summary ? master mode (continued) offset name bit pos
412 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each indi vidual register description. please refer to ?register access protection? on page 396 for details. some registers require synchronization when read and/or wr itten. synchronization is denoted by the write-synchronized or the read-synchronized property in each indi vidual register description. please refer to ?synchronization? on page 407 for details. some registers are enable-protected, meaning they can only be written when the i 2 c is disabled. enable-protection is denoted by the enable-protected property in each individual register description.
413 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.1 i 2 c slave register description 27.8.1.1 control a name: ctrla offset: 0x00 reset: 0x00000000 property: write-protected, enable-protected, write-synchronized z bit 31 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 30 ? lowtout: scl low time-out this bit enables the scl low time-out. if scl is held low for 25ms-35ms, the slave will release its clock hold, if enabled, and reset the internal state machine. any interrupts set at the time of time-out will remain set. 0: time-out disabled. 1: time-out enabled. this bit is not synchronized. z bits 29:22 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 21:20 ? sdahold[1:0]: sda hold time these bits define the sda hold time with respect to the negative edge of scl. bit3130292827262524 lowtout accessrr/wrrrrrr reset00000000 bit2322212019181716 sdahold[1:0] pinout access r r r/w r/w r r r r/w reset00000000 bit 15 14 13 12 11 10 9 8 accessrrrrrrrr reset00000000 bit76543210 runstdby mode[2:0]=100 enable swrst access r/w r r r/w r/w r/w r/w r/w reset00000000
414 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 27-3. sda hold time these bits are not synchronized. z bits 19:17 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 16 ? pinout: pin usage this bit sets the pin usage to either two- or four-wire operation: 0: 4-wire operation disabled 1: 4-wire operation enabled this bit is not synchronized. z bits 15:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 7 ? runstdby: run in standby this bit defines the functionality in standby sleep mode. 0: disabled ? all reception is dropped. 1: wake on address match, if enabled. this bit is not synchronized. z bits 6:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 4:2 ? mode[2:0]: operating mode these bits must be written to 0x04 to select the i 2 c slave serial communication interface of the sercom. these bits are not synchronized. z bit 1 ? enable: enable 0: the peripheral is disabled. 1: the peripheral is enabled. due to synchronization, there is delay from writing ctrla.enable until the peripheral is enabled/disabled. the value written to ctrl.enable will read back immediately and the synchronization busy bit in the status register (status.syncbusy) will be set. status.syncbusy will be cleared when the operation is complete. this bit is not enable-protected. z bit 0 ? swrst: software reset 0: there is no reset operation ongoing. 1: the reset operation is ongoing. writing a zero to this bit has no effect. value name description 0x0 dis disabled 0x1 75 50-100ns hold time 0x2 450 300-600ns hold time 0x3 600 400-800ns hold time
415 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 writing a one to this bit resets all registers in the serc om, except dbgctrl, to their initial state, and the ser- com will be disabled. writing a one to ctrla.swrst will always take precedence, meaning that all other writes in the same write-oper- ation will be discarded. due to synchronization, there is a delay from writing ctrla.swrst until the reset is complete. ctrla.swrst and status.syncbusy will both be cl eared when the reset is complete. this bit is not enable-protected.
416 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.1.2 control b name: ctrlb offset: 0x04 reset: 0x00000000 property: write-protected, enable-protected, write-synchronized z bits 31:19 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 18 ? ackact: acknowledge action 0: send ack 1: send nack the acknowledge action (ackact) bit defines the slave' s acknowledge behavior after an address or data byte is received from the master. the acknowledge action is ex ecuted when a command is written to the cmd bits. if smart mode is enabled (ctrlb.smen is one), the acknowl edge action is performed when the data register is read. this bit is not enable-protected. this bit is not write-synchronized. z bits 17:16 ? cmd[1:0]: command writing the command bits (cmd) triggers the slave operation as defined in table 27-4 . the cmd bits are strobe bits, and always read as zero. the operation is dependent on the slave interrupt flags, intflag.drdy and int- flag.amatch, in addition to status.dir (see table 27-4 ). bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 ackact cmd[1:0] accessrrrrrr/wr/wr/w reset00000000 bit151413121110 9 8 amode[1:0] smen accessr/wr/wrrrrrr/w reset00000000 bit76543210 accessrrrrrrrr reset00000000
417 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 all interrupt flags (intflag.drdy, intflag.amatch and intflag.prec) are automatically cleared when a command is given. this bit is not enable-protected. table 27-4. command description z bits 15:14 ? amode[1:0]: address mode these bits set the addressing mode according to table 27-5 . table 27-5. address mode description see the sercom datasheet for additional information. this bit is not write-synchronized. z bits 13:9 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 8 ? smen: smart mode enable this bit enables smart mode. when smart mode is enabl ed, acknowledge action is sent when data.data is read. 0: smart mode is disabled. 1: smart mode is enabled. this bit is not write-synchronized. cmd[1:0] dir action 0x0 x (no action) 0x1 x (reserved) 0x2 used to complete a transaction in response to a data interrupt (drdy) 0 (master write) execute acknowledge action succeeded by waiting for any start (s/sr) condition 1 (master read) wait for any start (s/sr) condition 0x3 used in response to an address interrupt (amatch) 0 (master write) execute acknowledge action succeeded by reception of next byte 1 (master read) execute acknowledge action succeeded by slave data interrupt used in response to a data interrupt (drdy) 0 (master write) execute acknowledge action succeeded by reception of next byte 1 (master read) execute a byte read operation followed by ack/nack reception value name description 0x0 mask the slave responds to the address writt en in addr.addr masked by the value in addr.addrmask (1) . 0x1 2_addrs the slave responds to the two unique addresses in addr.addr and addr.addrmask. 0x2 range the slave responds to the range of addresses between and including addr.addr and addr.addrmask. addr.addr is the upper limit. 0x3 - reserved.
418 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bits 7:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read.
419 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.1.3 interrupt enable clear this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable se registert (intenset). name: intenclr offset: 0x0c reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? drdy: data ready interrupt enable 0: the data ready interrupt is disabled. 1: the data ready interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the data ready bit, which disables the data ready interrupt. z bit 1 ? amatch: address match interrupt enable 0: the address match interrupt is disabled. 1: the address match interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the address match bit, which disables the address match interrupt. z bit 0 ? prec: stop received interrupt enable 0: the stop received interrupt is disabled. 1: the stop received interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the stop received bit, which disables the stop received interrupt. bit76543210 drdy amatch prec accessrrrrrr/wr/wr/w reset00000000
420 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.1.4 interrupt enable set this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear register (intenclr). name: intenset offset: 0x0d reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? drdy: data ready interrupt enable 0: the data ready interrupt is disabled. 1: the data ready interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the data ready bit, which enables the data ready interrupt. z bit 1 ? amatch: address match interrupt enable 0: the address match interrupt is disabled. 1: the address match interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the address match bit, which enables the address match interrupt. z bit 0 ? prec: stop received interrupt enable 0: the stop received interrupt is disabled. 1: the stop received interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the stop received bit, which enables the stop received interrupt. bit76543210 drdy amatch prec accessrrrrrr/wr/wr/w reset00000000
421 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.1.5 interrupt flag status and clear name: intflag offset: 0x0e reset: 0x00 property: - z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? drdy: data ready this flag is set when a i 2 c slave byte transmission is successfully co mpleted. the flag is cleared by hardware when either: z writing to the data register. z reading the data register with smart mode enabled. z writing a valid command to the cmd register. optionally, the flag can be cleared manually by writing a one to intflag.drdy. writing a zero to this bit has no effect. writing a one to this bit will clear the data ready interrupt flag. z bit 1 ? amatch: address match this flag is set when the i 2 c slave address match logic detects that a valid address has been received. the flag is cleared by hardware when ctrl.cmd is written. optionally the flag can be cleared manually by writing a one to intflag.amatch. when cleared, an ack/nack will be sent according to ctrlb.ackact. writing a zero to this bit has no effect. writing a one to this bit will clear the address match interrupt flag. z bit 0 ? prec: stop received this flag is set when a stop condition is detected for a transaction being processed. a stop condition detected between a bus master and another slave will not set this flag. this flag is cleared by hardware after a command is issued on the next address match. optionally, the flag can be cleared manually by writing a one to intflag.prec. writing a zero to this bit has no effect. writing a one to this bit will clear the stop received interrupt flag. bit 76543210 drdy amatch prec access rrrrrr/wr/wr/w reset 00000000
422 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.1.6 status name: status offset: 0x10 reset: 0x0000 property: - z bit 15 ? syncbusy: synchronization busy this bit is cleared when the synchronization of registers between the clock domains is complete. this bit is set when the synchronization of registers between clock domains is started. z bits 14:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 7 ? clkhold: clock hold the slave clock hold bit (status.clkhold) is set when the slave is holding the scl line low, stretching the i 2 c clock. software should consider this bit a read-only status flag that is set when intflag.drdy or int- flag.amatch is set. when the corresponding interrupt fl ag is cleared, this bit is also automatically cleared. z bit 6 ? lowtout: scl low time-out this bit is set if an scl low time-out occurs. this bit is cleared automatically if responding to a new start condition with ack or nack (write 3 to ctrlb. cmd) or when intfla g.amatch is cleared. 0: no scl low time-out has occurred. 1: scl low time-out has occurred. writing a zero to this bit has no effect. writing a one to this bit will clear the status. z bit 5 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 4 ? sr: repeated start when intflag.amatch is raised due to an address match, sr indicates a repeated start or start condition. 0: start condition on last address match 1: repeated start condition on last address match this flag is only valid while the intflag.amatch flag is one. z bit 3 ? dir: read / write direction the read/write direction (status.dir) bit stores the dire ction of the last address packet received from a master. bit 151413121110 9 8 syncbusy accessrrrrrrrr reset00000000 bit 76543210 clkhold lowtout sr dir rxnack coll buserr access r r/w r r r r r/w r/w reset00000000
423 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 0: master write operation is in progress. 1: master read operation is in progress. z bit 2 ? rxnack: received not acknowledge this bit indicates whether the last data packet sent was acknowledged or not. 0: master responded with ack. 1: master responded with nack. z bit 1 ? coll: transmit collision if set, the i 2 c slave was not able to transmit a high data or nack bit, the i 2 c slave will immediately release the sda and scl lines and wait for the next packet addressed to it. this flag is intended for the smbus address resolution prot ocol (arp). a detected collision in non-arp situations indicates that there has been a protocol violation, and should be treated as a bus error. note that this status will not trigger any interrupt, and should be checked by software to verify that the data were sent correctly. this bit is cleared automatically if res ponding to an address match with an ack or a nack (writing 0x3 to ctrlb.cmd), or intflag.amatch is cleared. 0: no collision detected on last data byte sent. 1: collision detected on last data byte sent. writing a zero to this bit has no effect. writing a one to this bit will clear the status. z bit 0 ? buserr: bus error the bus error bit (status.buserr) indicates that an illegal bus condition has occurred on the bus, regardless of bus ownership. an illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on the i 2 c bus lines. a start condition directly followed by a st op condition is one example of a protocol violation. if a time-out occurs during a frame, this is also cons idered a protocol violation, and will set status.buserr. this bit is cleared automatically if responding to an addr ess match with an ack or a nack (writing 0x3 to ctrlb.cmd) or intflag.amatch is cleared. 0: no bus error detected. 1: bus error detected. writing a one to this bit will clear the status. writing a zero to this bit has no effect.
424 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.1.7 address name: addr offset: 0x14 reset: 0x00000000 property: write-protected, enable-protected z bits 31:24 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 23:17 ? addrmask[6:0]: address mask the addrmask bits acts as a sec ond address match register, an address mask register or the lower limit of an address range, depending on the ctrlb.amode setting. z bits 16:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 7:1 ? addr[6:0]: address the slave address (addr) bits contain the i 2 c slave address used by the slave address match logic to determine if a master has addressed the slave. when using 7-bit addressing, the address register (addr.addr) represents the slave address. if using 10-bit addressing, the address match logic only suppor ts hardware address recognition of the first 2 bits of a 10-bit address. if writing addr.addr = "0b1111 0xx," 'xx' r epresents bits 9 and 8 or the slave address. the next byte received is bits 7 to 0 in the 10-bit address, and this must be handled by software. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 addrmask[6:0] accessr/wr/wr/wr/wr/wr/wr/w r reset00000000 bit151413121110 9 8 accessrrrrrrrr reset00000000 bit76543210 addr[6:0] gencen access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
425 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 when the address match logic detects a match, intflag. amatch is set and status.dir is updated to indicate whether it is a read or a write transaction. z bit 0 ? gencen: general call address enable writing a one to gencen enables general call address reco gnition. a general call address is an address of all zeroes with the direction bit written to zero (master write). 0: general call address recognition disabled. 1: general call address recognition enabled.
426 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.1.8 data name: data offset: 0x18 reset: 0x0000 property: write-synchronized, read-synchronized z bits 15:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 7:0 ? data[7:0]: data the slave data register i/o location (data.data) provides access to the master transmit and receive data buf- fers. reading valid data or writing data to be transmitt ed can be successfully done only when scl is held low by the slave (status.clkhold is set). an exception occurs when reading the last data byte after the stop condition has been received. accessing data.data auto-triggers i 2 c bus operations. the operation performed depends on the state of ctrlb.ackact, ctrlb.smen and the type of access (read/write). writing or reading data.data when not in smart mode does not require synchronization. bit151413121110 9 8 accessrrrrrrrr reset00000000 bit76543210 data[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
427 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.2 i 2 c master register description 27.8.2.1 control a name: ctrla offset: 0x00 reset: 0x00000000 property: write-protected, enable-protected, write-synchronized z bit 31 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 30 ? lowtout: scl low time-out this bit enables the scl low time-out. if scl is held low for 25ms-35ms, the master will release its clock hold, if enabled, and complete the current transaction. a stop condition will automatically be transmitted. intflag.sb or intflag.mb will be set as normal, but the clock hold will be released. the status.lowtout and status.buserr status bits will be set. 0: time-out disabled. 1: time-out enabled. this bit is not synchronized. z bits 29:28 ? inactout[1:0]: inactive time-out if the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus state logic will be set to idle. an inactive bus arise when either an i 2 c master or slave is holding the scl low. the available time-outs are given in table 27-6 . bit 3130292827262524 lowtout inactout[1:0] access r r/w r/w r/w r r r r reset00000000 bit 2322212019181716 sdahold[1:0] pinout access r r r/w r/w r r r r/w reset00000000 bit 151413121110 9 8 accessrrrrrrrr reset00000000 bit 76543210 runstdby mode[2:0]=101 enable swrst access r/w r r r/w r/w r/w r/w r/w reset00000000
428 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 enabling this option is necessary for smbus compatibility, but can also be used in a non-smbus set-up. table 27-6. inactive timout calculated time-out periods are based on a 100khz baud rate. these bits are not synchronized. z bits 27:22 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 21:20 ? sdahold[1:0]: sda hold time these bits define the sda hold time with respect to the negative edge of scl. table 27-7. sda hold time these bits are not synchronized. z bits 19:17 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 16 ? pinout: pin usage this bit set the pin usage to either two- or four-wire operation: 0: 4-wire operation disabled. 1: 4-wire operation enabled. this bit is not synchronized. z bits 15:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 7 ? runstdby: run in standby this bit defines the functionality in standby sleep mode. 0: gclk_sercomi_core is disabled and the i 2 c master will not operate in standy sleep mode. 1: gclk_sercomi_core is enabled in all sleep modes allowing the master to operate in standby sleep mode. this bit is not synchronized. value name description 0x0 dis disabled 0x1 55us 5-6 scl cycle time-out (50-60us) 0x2 105us 10-11 scl cycle time-out (100-110us) 0x3 205us 20-21 scl cycle time-out (200-210us) value name description 0x0 dis disabled 0x1 75ns 50-100ns hold time 0x2 450ns 300-600ns hold time 0x3 600ns 400-800ns hold time
429 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bits 6:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 4:2 ? mode[2:0]: operating mode these bits must be written to 0x5 to select the i 2 c master serial communication interface of the sercom. these bits are not synchronized. z bit 1 ? enable: enable 0: the peripheral is disabled. 1: the peripheral is enabled. due to synchronization, there is delay from writing ctrla.enable until the peripheral is enabled/disabled. the value written to ctrl.enable will read back immediately and the synchronization busy bit in the status register (status.syncbusy) will be set. status.syncbusy will be cleared when the operation is complete. this bit is not enable-protected. z bit 0 ? swrst: software reset 0: there is no reset operation ongoing. 1: the reset operation is ongoing. writing a zero to this bit has no effect. writing a one to this bit resets all registers in the serc om, except dbgctrl, to their initial state, and the ser- com will be disabled. writing a one to ctrla.swrst will always take precedence, meaning that all other writes in the same write-oper- ation will be discarded. due to synchronization there is a delay from writing ctrla.swrst until the reset is complete. ctrla.swrst and status.syncbusy will both be cl eared when the reset is complete. this bit is not enable-protected.
430 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.2.2 control b name: ctrlb offset: 0x04 reset: 0x00000000 property: write-protected, enable-protected, write-synchronized z bits 31:19 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 18 ? ackact: acknowledge action the acknowledge action (ackact) bit defines the i 2 c master's acknowledge behavior after a data byte is received from the i 2 c slave. the acknowledge action is executed when a command is written to ctrlb.cmd, or if smart mode is enabled (ctrlb.smen is wr itten to one), when data.data is read. 0: send ack. 1: send nack. this bit is not enable-protected. this bit is not write-synchronized. z bits 17:16 ? cmd[1:0]: command writing the command bits (cmd) triggers the master operation as defined in table 27-8 . the cmd bits are strobe bits, and always read as zero. the acknowledge action is only valid in master read mode. in master write mode, a command will only result in a repeated start or stop c ondition. the ctrlb.ackact bit and the cmd bits can be written at the same time, and then the acknowledge action will be updated before the command is triggered. bit3130292827262524 accessrrrrrrrr reset00000000 bit2322212019181716 ackact cmd[1:0] access r r r r r r/w r/w r/w reset00000000 bit151413121110 9 8 qcen smen accessrrrrrrrr/w reset00000000 bit76543210 accessrrrrrrrr reset00000000
431 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 commands can only be issued when the slave on bus interrupt flag (intflag.sb) or ma ster on bus interrupt flag (intflag.mb) is one. if cmd 0x1 is issued, a repeated start will be issued followed by the transmission of the current address in addr.addr. if another address is desired, addr.addr must be written instead of the cmd bits. this will trigger a repeated start followed by transmission of the new address. issuing a command will set status.syncbusy. table 27-8. command description these bits are not enable-protected. z bits 15:10 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 9 ? qcen: quick command enable setting the quick command enable bit (qcen) enables quick command. 0: quick command is disabled. 1: quick command is enabled. this bit is not write-synchronized. z bit 8 ? smen: smart mode enable this bit enables smart mode. when smart mode is enabl ed, acknowledge action is sent when data.data is read. 0: smart mode is disabled. 1: smart mode is enabled. this bit is not write-synchronized. z bits 7:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. cmd[1:0] dir action 0x0 x (no action) 0x1 x execute acknowledge action succeeded by repeated start 0x2 0 (write) no operation 1 (read) execute acknowledge action succeeded by a byte read operation 0x3 x execute acknowledge action succeed ed by issuing a stop condition
432 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.2.3 debug control name: dbgctrl offset: 0x08 reset: 0x00 property: write-protected z bits 7:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? dbgstop: debug stop mode this bit controls functionality when the cpu is halted by an external debugger. 0: the baud-rate generator continues normal operati on when the cpu is halted by an external debugger. 1: the baud-rate generator is halted when the cpu is halted by an external debugger. bit76543210 dbgstop accessrrrrrrrr/w reset00000000
433 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.2.4 baud rate name: baud offset: 0x0a reset: 0x0000 property: write-protected, enable-protected z bits 15:8 ? baudlow[7:0]: master baud rate low if the master baud rate low bit group (baudlow) has a non-zero value, the scl low time will be described by the value written. for more information on how to calculate the frequency, see ?sercom i2c ? sercom inter-integrated circuit? on page 394 . z bits 7:0 ? baud[7:0]: master baud rate the master baud rate bit group (baud) is used to deriv e the scl high time if baud.baudlow is non-zero. if baud.baudlow is zero, baud will be used to generate both high and low periods of the scl. for more information on how to calculate the frequency, see ?sercom i2c ? sercom inter-integrated circuit? on page 394 . bit151413121110 9 8 baudlow[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 baud[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
434 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.2.5 interrupt enable clear this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable set register (intenset). name: intenclr offset: 0x0c reset: 0x00 property: write-protected z bits 7:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? sb: slave on bus interrupt enable 0: the slave on bus interrupt is disabled. 1: the slave on bus interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the slave on bus bit, which disables the slave on bus interrupt. z bit 0 ? mb: master on bus interrupt enable 0: the master on bus interrupt is disabled. 1: the master on bus interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the master on bus bit, which disables the master on bus interrupt. bit76543210 sb mb accessrrrrrrr/wr/w reset00000000
435 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.2.6 interrupt enable set this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear register (intenclr). name: intenset offset: 0x0d reset: 0x00 property: write-protected z bits 7:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? sb: slave on bus interrupt enable 0: the slave on bus interrupt is disabled. 1: the slave on bus interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the slave on bus bit, which enables the slave on bus interrupt. z bit 0 ? mb: master on bus interrupt enable 0: the master on bus interrupt is disabled. 1: the master on bus interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the master on bus bit, which enables the master on bus interrupt. bit76543210 sb mb accessrrrrrrr/wr/w reset00000000
436 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.2.7 interrupt flag status and clear name: intflag offset: 0x0e reset: 0x00 property: - z bits 7:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? sb: slave on bus the slave on bus flag (sb) is set when a byte is successfully received in master read mode, i.e., no arbitration lost or bus error occurred during the operation. when this flag is set, the master forces the scl line low, stretching the i 2 c clock period. the scl line will be released and sb will be cleared on one of the following actions: z writing to addr.addr z writing to data.data z reading data.data when smart mode is enabled (ctrlb.smen) z writing a valid command to ctrlb.cmd writing a one to this bit location will clear the sb flag. the transaction will not continue or be terminated until one of the above actions is performed. writing a zero to this bit has no effect. z bit 0 ? mb: master on bus the master on bus flag (mb) is set when a byte is transmitt ed in master write mode. the flag is set regardless of the occurrence of a bus error or an arbitration lost conditi on. mb is also set when arbitration is lost during sending of nack in master read mode, and when issuing a start cond ition if the bus state is unknown. when this flag is set and arbitration is not lost, the master forces the scl line low, stretching the i 2 c clock period. the scl line will be released and mb will be cleared on one of the following actions: z writing to addr.addr z writing to data.data z reading data.data when smart mode is enabled (ctrlb.smen) z writing a valid command to ctrlb.cmd if arbitration is lost, writing a one to this bit location will clear the mb flag. if arbitration is not lost, writing a one to this bit location will clear the mb flag. the transaction will not continue or be terminated until one of the above actions is performed. writing a zero to this bit has no effect. bit76543210 sb mb accessrrrrrrr/wr/w reset00000000
437 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.2.8 status name: status offset: 0x10 reset: 0x0000 property: write-synchronized z bit 15 ? syncbusy: synchronization busy this bit is cleared when the synchronization of registers between the clock domains is complete. this bit is set when the synchronization of registers between clock domains is started. z bits 14:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 7 ? clkhold: clock hold the master clock hold flag (status.clkhold) is set when the master is holding the scl line low, stretching the i 2 c clock. software should consider this bit a read-only status flag that is set when intflag.sb or int- flag.mb is set. when the corresponding interrupt flag is cleared and the next operation is given, this bit is automatically cleared. writing a zero to this bit has no effect. writing a one to this bit has no effect. this bit is not write-synchronized. z bit 6 ? lowtout: scl low time-out this bit is set if an scl low time-out occurs. writing a one to this bit location will clear status.lowtout. normal use of the i 2 c interface does not require the lowtout flag to be cleared by this method. this flag is automatically cleared when either: z writing to addr.addr z writing to data.data z reading data.data when smart mode is enabled (ctrlb.smen) z writing a valid command to ctrlb.cmd writing a zero to this bit has no effect. this bit is not write-synchronized. z bits 5:4 ? busstate[1:0]: bus state these bits indicate the current i 2 c bus state as defined in table 27-9 . after enabling the sercom as an i 2 c mas- ter, the bus state will be unknown. bit151413121110 9 8 syncbusy accessrrrrrrrr reset00000000 bit76543210 clkhold lowtout busstate[1:0] rxnack arblost buserr access r r/w r r/w r r r/w r/w reset00000000
438 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 27-9. bus state when the master is disabled, the bus-state is unknown. when in the unknown state, writing 0x1 to busstate forces the bus state into the idle state. the bus state cannot be forced into any other state. writing status.busstate to id le will set status.syncbusy. z bit 3 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 2 ? rxnack: received not acknowledge this bit indicates whether the last address or data packet sent was acknowledged or not. 0: slave responded with ack. 1: slave responded with nack. writing a zero to this bit has no effect. writing a one to this bit has no effect. this bit is not write-synchronized. z bit 1 ? arblost: arbitration lost the arbitration lost flag (status.arblost) is set if ar bitration is lost while transmitting a high data bit or a nack bit, or while issuing a start or repeated start condi tion on the bus. the master on bus interrupt flag (int- flag.mb) will be set when status.arblost is set. writing the addr.addr register will automatically clear status.arblost. writing a zero to this bit has no effect. writing a one to this bit will clear it. this bit is not write-synchronized. z bit 0 ? buserr: bus error the bus error bit (status.buserr) indicates that an illegal bus condition has occurred on the bus, regardless of bus ownership. an illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on the i 2 c bus lines. a start condition directly followed by a st op condition is one example of a protocol violation. if a time-out occurs during a frame, this is also considered a protocol violation, and will set buserr. if the i 2 c master is the bus owner at the time a bus erro r occurs, status.arblost and intflag.mb will be set in addition to buserr. writing the addr.addr register will automatically clear the buserr flag. writing a zero to this bit has no effect. writing a one to this bit will clear it. this bit is not write-synchronized. value name description 0x0 unknown the bus state is unknown to the i 2 c master and will wait for a stop condition to be detected or wait to be forced into an idlestate by software 0x1 idle the bus state is waiting for a transaction to be initialized 0x2 owner the i 2 c master is the current owner of the bus 0x3 busy some other i 2 c master owns the bus
439 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.2.9 address name: addr offset: 0x14 reset: 0x0000 property: write-synchronized z bits 15:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 7:0 ? addr[7:0]: address when addr is written, the consecutive operation will depend on the bus state: unknown: intflag.mb and status.buser r are set, and the operation is terminated. busy: the i 2 c master will await further operation until the bus becomes idle. idle: the i 2 c master will issue a start condition followed by the address written in addr. if the address is acknowl- edged, scl is forced and held low, and stat us.clkhold and intflag.mb are set. owner: a repeated start sequence will be performed. if the previous transaction was a read, the acknowledge action is sent before the repeated start bus condition is issued on the bus. writing addr to issue a repeated start is performed while intflag.mb or intflag.sb is set. regardless of winning or loosing arbitration, the entire addr ess will be sent. if arbitration is lost, only ones are transmitted from the point of loosing arbitration and the rest of the address length. status.buserr, stat us.arblost, intflag.mb and intflag.sb will be cleared when addr is written. the addr register can be read at any time without inte rfering with ongoing bus activity,as a read access does not trigger the master logic to perform any bus protocol related operations. the i 2 c master control logic uses bit 0 of addr as the bus protocol?s read/write flag (r/w); 0 for write and 1 for read. bit151413121110 9 8 accessrrrrrrrr reset00000000 bit76543210 addr[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
440 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 27.8.2.10 data name: data offset: 0x18 reset: 0x0000 property: write-synchronized, read-synchronized z bits 15:8 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 7:0 ? data[7:0]: data the master data register i/o location (data) provides access to the master transmit and receive data buffers. reading valid data or writing data to be transmitted can be successfully done only when scl is held low by the master (status.clkhold is set). an exception occurs when reading the last data byte after the stop condition has been sent. accessing data.data auto-triggers i 2 c bus operations. the operation performed depends on the state of ctrlb.ackact, ctrlb.smen and the type of access (read/write). writing or reading data.data when not in smart mode does not require synchronization. bit151413121110 9 8 accessrrrrrrrr reset00000000 bit76543210 data[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
441 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28. tc ? timer/counter 28.1 overview the tc consists of a counter, a prescaler, compare/capture channels and control logic. the counter can be set to count events, or it can be configured to count clock pulses. t he counter, together with the compare/capture channels, can be configured to timestamp input events, allowing capture of frequency and pulse width. it can also perform waveform generation, such as frequency generation and pulse-width modulation (pwm) . 28.2 features z selectable configuration z 8-, 16- or 32-bit tc, wit h compare/capture channels z waveform generation z frequency generation z single-slope pulse-width modulation z input capture z event capture z frequency capture z pulse-width capture z one input event z interrupts/output events on: z counter overflow/underflow z compare match or capture z internal prescaler
442 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.3 block diagram figure 28-1. timer/counter block diagram per p e r prescaler p r e s c a l e r control logic c o n t r o l l o g i c control logic c o n t r o l l o g i c waveform w a v e f o r m generation g e n e r a t i o n count c o u n t cc0 c c 0 base counter b a s e c o u n t e r counter c o u n t e r compare / capture c o m p a r e / c a p t u r e top t o p zero z e r o = 0 = 0 = match m a t c h update u p d a t e event e v e n t = ovf/unf o v f / u n f (int req.) ( i n t r e q . ) err e r r (int req.) ( i n t r e q . ) wox out w o x o u t ccx c c x (int req.) ( i n t r e q . ) count c o u n t clear c l e a r load l o a d direction d i r e c t i o n
443 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.4 signal description refer to ?i/o multiplexing and considerations? on page 15 for details on the pin mapping for this peripheral. one signal can be mapped on several pins. 28.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 28.5.1 i/o lines using the tc?s i/o lines requires the i/o pins to be configured. refer to ?port? on page 289 for details. 28.5.2 power management the tc can continue to operate in any sleep mode where the selected source clock is running. the tc interrupts can be used to wake up the device from sleep modes. the events can trigger other operations in the system without exiting sleep modes. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. 28.5.3 clocks the tc bus clock (clk_tcx_apb, where x represents the specific tc instance number) can be enabled and disabled in the power manager, and the default state of clk_tcx_apb can be found in the peripheral clock masking section in ?pm ? power manager? on page 105 . the different tc instances are paired, even and odd, starti ng from tc0, and use the same generic clock, gclk_tcx. this means that the tc instances in a tc pair cannot be set up to use different gclk_tcx clocks this generic clock is asynchronous to the user interface cl ock (clk_tcx_apb). due to th is asynchronicity, accessing certain registers will require synchronization between the clock domains. refer to ?synchronization? on page 452 for further details. 28.5.4 interrupts the interrupt request line is connected to the interrupt controll er. using the tc interrupts requires the interrupt controller to be configured first. refer to ?nested vector interrupt controller? on page 28 for details. 28.5.5 events to use the tc event functionality, the corresponding events need to be configured in the event system. refer to ?evsys ? event system? on page 314 for details. 28.5.6 debug operation when the cpu is halted in debug mode the tc will halt normal operation. the tc can be forced to continue operation during debugging. refer to the dbgctrl register for details. 28.5.7 register access protection all registers with write-access are optionally write-protect ed by the peripheral access controller (pac), except the following registers: z interrupt flag register (intflag) z status register (status) signal name type description wo[1:0] digital output waveform output
444 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z read request register (readreq) z count register (count) z period register (per) z compare/capture value registers (ccx) write-protection is denoted by the write-protection property in the register description. when the cpu is halted in debug mode, all wr ite-protection is automatically disabled. write-protection does not apply for accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details. 28.5.8 analog connections not applicable. 28.6 functional description 28.6.1 principle of operation the counter in the tc can be set to count on events from the event system, or on the gclk_tcx frequency. the pulses from gclk_tcx will go through the prescaler, w here it is possible to divide the frequency down. the value in the counter is passed to the compare/capture channels, where it can either be compared with user defined values or captured on a predefined event. the tc can be configured as an 8-, 16- or 32-bit counter . which mode is chosen will determine the maximum range of the counter. the counter range combined with the operat ing frequency will determine the maximum time resolution achievable with the tc peripheral. the tc can be set to count up or down. by default, the counter will operate in a continuous mode, where the counter will wrap to the zero respectively top value it counts from when reaching the top respectively zero. when one of the compare/capture channels is used in compare mode, the tc can be used for waveform generation. upon a match between the counter and the value in one or more of the compare/capture value registers (ccx), one or more output pins on the device can be set to toggle. the ccx registers and the counter can thereby be used in frequency generation and pwm generation. capture mode can be used to automatically capture the period and pulse width of signals. 28.6.2 basic operation 28.6.2.1 initialization the following register is enable-protected, meaning that it can only be written when the tc is disabled (ctrla.enable is zero): z control a register (ctrla), except the run stand by (runstdby), enable (enable) and software reset (swrst) bits the following bits are enable-protected: z event action bits in the event control register (evctrl.evact) enable-protected bits in the ctrla register can be written at the same time as ctrla.enable is written to one, but not at the same time as ctrla.enable is written to zero. before the tc is enabled, it must be configured, as outlined by the following steps: z the tc bus clock (clk_tcx_apb) must be enabled z the mode (8, 16 or 32 bits) of the tc must be selected in the tc mode bit group in the control a register (ctrla.mode). the default mode is 16 bits
445 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z one of the wavegen modes must be selected in the waveform generation operation bit group in the control a register (ctrla.wavegen) z if the gclk_tcx frequency used should be prescaled, this can be selected in the prescaler bit group in the control a register (ctrla.prescaler) z if the prescaler is used, one of the presync modes must be chosen in the prescaler and counter synchronization bit group in the cont rol a register (ctrla.presync) z one-shot mode can be selected by writing a one to the one-shot bit in the control b set register (ctrlbset.oneshot) z if the counter should count down from the top value, write a one to the counter direction bit in the control b set register (ctrlbset.dir) z if capture operations are to be used, the individual channels must be enabled for capture in the capture channel x enable bit group in the control c register (ctrlc.cpten) z the waveform output for individual channels can be inverted using the output waveform invert enable bit group in the control c register (ctrlc.inven) 28.6.2.2 enabling, disabling and resetting the tc is enabled by writing a one to the enable bit in the c ontrol a register (ctrla.enable). the tc is disabled by writing a zero to ctrla.enable. the tc is reset by writing a one to the software reset bit in the control a register (ctrla .swrst). all registers in the tc, except dbgctrl, will be reset to their initial state, and the tc will be disabled. refer to the ctrla register for details. the tc should be disabled before the tc is reset to avoid undefined behavior. 28.6.2.3 prescaler selection as seen in figure 28-2 , the gclk_tc clock is fed into the internal prescaler. prescaler output intervals from 1 to 1/1024 are available. for a complete list of available prescaler outputs, see the register description for the prescaler bit group in the control a register (ctrla.prescaler). the prescaler consists of a counter that counts to the selected prescaler value, whereupon the output of the prescaler toggles. when the prescaler is set to a value greater than one, it is necessary to choose whether the prescaler should reset its value to zero or continue counting from its current value on the occurrence of an overflow or underflow. it is also necessary to choose whether the tc counter should wrap around on the next gclk_tc clock pulse or the next prescaled clock pulse (clk_tc_cnt of figure 28-2 ). to do this, use the prescaler and counter synchronization bit group in the control a r egister (ctrla.presync). if the counter is set to count events from the event system, these will not pass through the prescaler, as seen in figure 28-2 . figure 28-2. prescaler 28.6.2.4 tc mode the counter mode is selected with the tc mode bit group in the control a register (ctrla.mode). by default, the counter is enabled in the 16-bit counter mode. prescaler gclk_tc / {1,2,4,8,64,256,1024} gclk_tc prescaler cnt clk_tc_cnt evact event
446 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 three counter modes are available: z count8: the 8-bit tc has its own period register (per). this register is used to store the period value that can be used as the top value for waveform generation. z count16: this is the default counter mode. ther e is no dedicated period register in this mode. z count32: this mode is achieved by pairing two 16- bit tc peripherals. this pairing is explained in ?clocks? on page 443 . the even-numbered tc instance will act as ma ster to the odd-numbered tc peripheral,which will act as a slave. the slave status of the slave is indicated by reading the slave bit in the status register (status.slave). the registers of the slave will not reflect the registers of the 32-bit counter. writing to any of the slave registers will not affect the 32-bit counter. normal access to the slave count and ccx registers is not allowed. 28.6.2.5 counter operations the counter can be set to count up or down. when the counter is counting up and the top value is reached, the counter will wrap around to zero on the next clock cycle. when counting down, the counter will wrap around to the top value when zero is reached. for one-shot mode, the counter will continue to count after a wraparound occurs. to set the counter to count down, write a one to the direction bit in the control b set regist er (ctrlbset.dir). to count up, write a one to the direction bit in t he control b clear register (ctrlbclr.dir). each time the counter reaches the top value or zero, it will set the overflow interrupt flag in the interrupt flag status and clear register (intflag.ovf). it is also possible to generate an event on overflow or underflow when the overflow/underflow event output enable bit in t he event control register (evctrl.ovfeo) is one. the counter value can be read from the counter value regi ster (count) or a new value can be written to the count register. figure 28-3 gives an example of writing a new counter value. the count value will always be zero when starting the tc, unless some other value has been written to it or the tc has been stopped at some value other than zero. figure 28-3. counter operation stop command on the stop command, which can be evoked in the command bi t group in the control b set register (ctrlbset.cmd), the counter will retain its current value. all waveforms ar e cleared. the counter stops counting, and the stop bit in the status register is set (status.stop). retrigger command and event action retriggering can be evoked either as a software command, us ing the retrigger command in the control b set register (ctrlbset.cmd), or as a retrigger ev ent action, using the event action bit group in the event control register (evctrl.evact). dir count top count written direction change period (t) bot "update "
447 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 when a retrigger is evoked while the counter is running, t he counter will wrap to the top value or zero, depending on the counter direction.. when a retrigger is evoked with the counter stopped, the counter will continue counting from the value in the count register. note: when retrigger event action is configured and enabled as an event action, enabling the counter will not start the counter. the counter will start at the next incoming event and restart on any following event. count event action when the count event action is configured, every new inco ming event will make the counter increment or decrement, depending on the state of the direction bit (ctrlbset.dir). start event action when the tc is configured with a start event action in the evctrl.evact bit group, enabling the tc does not make the counter start; the start is postponed until the next input event or software retrigger action. when the counter is running, an input event has not effect on the counter. 28.6.2.6 compare operations when using the tc with the compare/capture value regist ers (ccx) configured for compare operation, the counter value is continuously compared to the values in the ccx registers. this can be used for timer or waveform operation. waveform output operations the compare channels can be used for waveform generation on the corresponding i/o pins. to make the waveform visible on the connected pin, the following requirements must be fulfilled: 1. choose a waveform generation operation 2. optionally, invert the waveform output by writing the corresponding output waveform invert enable bit in the con- trol c register (ctrlc.invx) 3. enable the corresponding multiplexor in the port the counter value is continuously compared with each ccx available. when a compare match occurs, the match or capture channel x interrupt flag in the interrupt flag status and clear register (intflag.mcx) is set on the next zero-to- one transition of clk_tc_cnt (see figure 28-4 ). an interrupt and/or event can be generated on such a condition when intenset.mcx and/or evctrl.mceox is one. one of four configurations in the waveform generation oper ation bit group in the control a register (ctrla.wavegen) must be chosen to perform waveform generation. this will influence how the waveform is generated and impose restrictions on the top value. the four configurations are: z normal frequency (nfrq) z match frequency (mfrq) z normal pwm (npwm) z match pwm (mpwm) when using npwm or nfrq, the top value is determined by t he counter mode. in 8-bit mode, the period register (per) is used as the top value and the top value can be changed by writing to the per register. in 16- and 32-bit mode, the top value is fixed to the maximum value of the counter. z frequency operation when nfrq is used, the output waveform (wo[x]) toggles every time ccx and the counter are equal, and the interrupt flag corresponding to that channel will be set.
448 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 28-4. normal frequency operation when mfrq is used, the value in cc0 will be used as th e top value and wo[0] will toggle on every overflow/underflow. figure 28-5. match frequency operation z pwm operation in pwm operation, the ccx registers control the duty cycle of the waveform generator output. figure 28-6 shows how the wo[x] output is set at a start or a compare match between the count value and the top value, and cleared on the compare match between the count value and ccx register value. count zero "wraparound " top cnt written ccx wo[x] count " wraparound " top count written direction change period (t) zero wo[0]
449 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 28-6. normal pwm operation in match operation, compare/capture register cc0 is used as the top value, and in this case wo[0] will toggle on every overflow/underflow. the following equation is used to calculate the exact period for a single-slope pwm (r pwm_ss ) waveform: where n represent the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024). changing the top value changing the top value while the counter is running is possible. if a new top value is written when the counter value is close to zero and counting down, the counter can be reloaded with the previous top value, due to synchronization delays. if this happens, the counter will count one extra cycle before the new top value is used. figure 28-7. changing the top value when counting down count top period (t) "match " zero wo[x] ccn= bot cc n ccn= top "wraparound " r pwm_ss top 1 + () log 2 () log ---------------------------------- = f pwm_ss f clk_tc ntop 1 + () ------------------------------ = count max "reload" "write" zero new top value that is higher than current count new top value that is lower than current count
450 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 when counting up a change from a top value that is lower relati ve to the old top value can make the counter miss this change if the counter value is larger than the new top value when the change occurred. this will make the counter count to the max value. an example of this can be seen in figure 28-8 . figure 28-8. changing the top value when counting up 28.6.2.7 capture operations to enable and use capture operations, the event line into the tc must be enabled using the tc event input bit in the event control register (evctrl.tcei). the capture channel s to be used must also be enabled in the capture channel x enable bit group in the control c register (c trlc.cptenx) before capture can be performed. event capture action the compare/capture channels can be used as input capture channels to capture any event from the event system and give them a timestamp. because all capture channels us e the same event line, only one capture channel should be enabled at a time when performing event capture. figure 28-9 shows four capture events for one capture channel. figure 28-9. input capture timing when the capture interrupt flag is set and a new capture event is detected, there is nowhere to store the new timestamp. as a result, the error interrupt flag in the interrupt flag status and clear register (intflag.err) is set. count max counter wraparound " wraparound " "write" zero new top value that is lower than current count new top value that is higher than current count events count top zero capture 0 capture 1 capture 2 capture 3
451 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 period and pulse-width capture action the tc can perform two input captures and restart the count er on one of the edges. this enables the tc to measure the pulse width and period. this can be used to characterize the frequency and duty cycle of an input signal: when using ppw event action, the period (t) will be captured into cc0 and the pulse width (tp) in cc1. in pwp event action, the pulse width (tp) will be capt ured in cc0 and the period (t) in cc1. selecting pwp (pulse-width, period) or ppw (period, pulse-width) in the event action bit group in the event control register (evctrl.evact) enables the tc to performs two capture actions, one on the rising edge and one on the falling edge. the tc inverted event input in the event control register (evctrl.tcinv) is used to select whether the wraparound should occur on the rising edge or the falling edge. if evct rl.tcinv is written to one, the wraparound will happen on the falling edge. the event source to be captured must be an asynchronous event. to fully characterize the frequency and duty cycle of the input signal, activate capture on cc0 and cc1 by writing 0x3 to the capture channel x enable bit group in the contro l c register (ctrlc.cpten ). when only one of these measurements is required, the second channel can be used for other purposes. the tc can detect capture overflow of the input captur e channels. when the capture interrupt flag is set and a new capture event is detected, there is nowhere to store the new timestamp. asa result, intflag.err is set. 28.6.3 additional features 28.6.3.1 one-shot operation when one-shot operation is enabled, the counter automatic ally stops on the next counter overflow or underflow condition. when the counter is stopped, status.stop is aut omatically set by hardware and the waveform outputs are set to zero. one-shot operation can be enabled by writing a one into the one-shot bit in the control b set register (ctrlbset.oneshot) and disabled by writing a one to the one-shot bit in the control b clear register (ctrlbclr.oneshot). when enabled, it will count until an overflow or underflow occurs. the one-shot operation can be restarted with a retrigger command, a retrigger event or a start event. when the counter restarts its operation, the stop bit in the st atus register (status.stop) is automatically cleared by hardware. 28.6.4 interrupts the tc has the following interrupt sources: z overflow/underflow: ovf z compare or capture channels z capture overflow error: err z synchronization ready: syncrdy each interrupt source has an interrupt flag associated with i t. the interrupt flag in the interrupt flag status and clear register (intflag) is set when the interrupt condition occu rs. each interrupt can be individually enabled by writing a one to the corresponding bit in the interrupt enable set regi ster (intenset), and disabled by writing a one to the corresponding bit in the interrupt enable clear register (int enclr). an interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the tc is reset. see the intflag register for details on how to clear interrupt flags. f 1 t -- - = dutycycle tp t ---- - =
452 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 the tc has one common interrupt request line for all the interr upt sources. the user must read the intflag register to determine which interrupt condition is present. note that inte rrupts must be globally enabled for interrupt requests to be generated. refer to ?nested vector interrupt controller? on page 28 for details. 28.6.5 events the tc can generate the following output events: z overflow/underflow (ovf) z match or capture (mc) writing a one to an event output bit in the event control register (evctrl . mceo) enables the corresponding output event. writing a zero to this bit disables the corresponding output event. to enable one of the following event actions, writ e to the event action bit group (evctrl.evact). z start the counter z retrigger counter z increment or decrement counter (depends on counter direction) z capture event z capture period z capture pulse width writing a one to the tc event input bit in the event cont rol register (evctrl.tcei) enables input events to the tc. writing a zero to this bit disables input events to the tc. refer to ?evsys ? event system? on page 314 for details on configuring the event system. 28.6.6 sleep mode operation the tc can be configured to operate in any sleep mode. to be able to run in standby, the runstdby bit in the control a register (ctrla.runstdby) must be wr itten to one. the tc can wake up the device using interrupts from any sleep mode or perform actions through the event system. 28.6.7 synchronization due to the asynchronicity between clk_tcx_apb and gc lk_tcx some registers must be synchronized when accessed. a register can require: z synchronization when written z synchronization when read z synchronization when written and read z no synchronization when executing an operation that requires synchronization, the synchronization busy bit in the status register(status.syncbusy) will be set immediately, and cleared when synchronization is complete. the synchronization ready interrupt can be used to signal when sync is complete. this can be accessed via the synchronization ready interrupt flag in the interrupt flag status and clear register (intflag.syncrdy). if an operation that requires synchronization is executed wh ile status.syncbusy is one, the bus will be stalled. all operations will complete successfully, but the cpu will be stalled and interrupts will be pending as long as the bus is stalled. the following bits need synchronization when written: z software reset bit in the control a register (ctrla.swrst) z enable bit in the control a register (ctrla.enable) write-synchronization is denoted by the write-synchronized property in the register description. the following registers need synchronization when written: z control b clear register (ctrlbclr) z control b set register (ctrlbset)
453 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z control c register (ctrlc) z count value register (count) z period value register (period) z compare/capture value registers (ccx) write-synchronization is denoted by the write-synchronized property in the register description. the following registers need synchronization when read: z control b clear register (ctrlbclr) z control b set register (ctrlbset) z control c register (ctrlc) z count value register (count) z period value register (period) z compare/capture value registers (ccx) read-synchronization is denoted by the read-synchronized property in the register description.
454 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.7 register summary table 28-1. register summar y ? 8-bit mode registers offset name bit pos. 0x00 ctrla 7:0 wavegen[1:0] mode[1:0] enable swrst 0x01 15:8 prescsync[1:0] runstdby prescaler[2:0] 0x02 readreq 7:0 addr[4:0] 0x03 15:8 rreq rcont 0x04 ctrlbclr 7:0 cmd[1:0] oneshot dir 0x05 ctrlbset 7:0 cmd[1:0] oneshot dir 0x06 ctrlc 7:0 cpten1 cpten0 inven1 inven0 0x07 reserved 0x08 dbgctrl 7:0 dbgrun 0x09 reserved 0x0a evctrl 7:0 tcei tcinv evact[2:0] 0x0b 15:8 mceo1 mceo0 ovfeo 0x0c intenclr 7:0 mc1 mc0 syncrdy err ovf 0x0d intenset 7:0 mc1 mc0 syncrdy err ovf 0x0e intflag 7:0 mc1 mc0 syncrdy err ovf 0x0f status 7:0 syncbusy slave stop 0x10 count 7:0 count[7:0] 0x11 reserved 0x12 reserved 0x13 reserved 0x14 per 7:0 per[7:0] 0x15 reserved 0x16 reserved 0x17 reserved 0x18 cc0 7:0 cc[7:0] 0x19 cc1 7:0 cc[7:0] 0x1a reserved 0x1b reserved 0x1c reserved 0x1d reserved 0x1e reserved 0x1f reserved
455 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 28-2. register summary ? 16-bit mode registers offset name bit pos. 0x00 ctrla 7:0 wavegen[1:0] mode[1:0] enable swrst 0x01 15:8 prescsync[1:0] runstdby prescaler[2:0] 0x02 readreq 7:0 addr[4:0] 0x03 15:8 rreq rcont 0x04 ctrlbclr 7:0 cmd[1:0] oneshot dir 0x05 ctrlbset 7:0 cmd[1:0] oneshot dir 0x06 ctrlc 7:0 cpten1 cpten0 inven1 inven0 0x07 reserved 0x08 dbgctrl 7:0 dbgrun 0x09 reserved 0x0a evctrl 7:0 tcei tcinv evact[2:0] 0x0b 15:8 mceo1 mceo0 ovfeo 0x0c intenclr 7:0 mc1 mc0 syncrdy err ovf 0x0d intenset 7:0 mc1 mc0 syncrdy err ovf 0x0e intflag 7:0 mc1 mc0 syncrdy err ovf 0x0f status 7:0 syncbusy slave stop 0x10 count 7:0 count[7:0] 0x11 15:8 count[15:8] 0x12 reserved 0x13 reserved 0x14 reserved 0x15 reserved 0x16 reserved 0x17 reserved 0x18 cc0 7:0 cc[7:0] 0x19 15:8 cc[15:8] 0x1a cc1 7:0 cc[7:0] 0x1b 15:8 cc[15:8] 0x1c reserved 0x1d reserved 0x1e reserved 0x1f reserved
456 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 28-3. register summary ? 32-bit mode registers offset name bit pos. 0x00 ctrla 7:0 wavegen[1:0] mode[1:0] enable swrst 0x01 15:8 prescsync[1:0] runstdby prescaler[2:0] 0x02 readreq 7:0 addr[4:0] 0x03 15:8 rreq rcont 0x04 ctrlbclr 7:0 cmd[1:0] oneshot dir 0x05 ctrlbset 7:0 cmd[1:0] oneshot dir 0x06 ctrlc 7:0 cpten1 cpten0 inven1 inven0 0x07 reserved 0x08 dbgctrl 7:0 dbgrun 0x09 reserved 0x0a evctrl 7:0 tcei tcinv evact[2:0] 0x0b 15:8 mceo1 mceo0 ovfeo 0x0c intenclr 7:0 mc1 mc0 syncrdy err ovf 0x0d intenset 7:0 mc1 mc0 syncrdy err ovf 0x0e intflag 7:0 mc1 mc0 syncrdy err ovf 0x0f status 7:0 syncbusy slave stop 0x10 count 7:0 count[7:0] 0x11 15:8 count[15:8] 0x12 23:16 count[23:16] 0x13 31:24 count[31:24] 0x14 reserved 0x15 reserved 0x16 reserved 0x17 reserved 0x18 cc0 7:0 cc[7:0] 0x19 15:8 cc[15:8] 0x1a 23:16 cc[23:16] 0x1b 31:24 cc[31:24] 0x1c cc1 7:0 cc[7:0] 0x1d 15:8 cc[15:8] 0x1e 23:16 cc[23:16] 0x1f 31:24 cc[31:24]
457 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each individual register des cription. please refer to the register access protection section and the pac chapter for details. some registers require synchronization when read and/or wr itten. synchronization is denoted by the write-synchronized or read-synchronized property in each indi vidual register description. refer to the synchronization section for details. some registers are enable-protected, meaning they can only be written when the tc is disabled. enable-protection is denoted by the enable-protected property in each individual register description.
458 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.1 control a name: ctrla offset: 0x00 reset: 0x0000 property: write-protected, enable-protected, write-synchronized z bits 15:14 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 13:12 ? prescsync[1:0]: prescal er and counter synchronization these bits select whether the counter should wrap ar ound on the next gclk_tcx clock or the next prescaled gclk_tcx clock. it also makes it possible to reset the prescaler. the options are as shown in table 28-4 . these bits are not synchronized. table 28-4. prescaler and counter synchronization z bit 11 ? runstdby: run in standby this bit is used to keep the tc running in standby mode: 0: the tc is halted in standby. 1: the tc continues to run in standby. this bit is not synchronized. z bits 10:8 ? prescaler[2:0]: prescaler these bits select the counter prescaler factor, as shown in table 28-5 . these bits are not synchronized. bit151413121110 9 8 prescsync[1:0] runstd by prescaler[2:0] access r r r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 wavegen[1:0] mode[1:0] enable swrst access r r/w r/w r r/w r/w r/w r/w reset00000000 value name description 0x0 gclk reload or reset the counter on next generic clock 0x1 presc reload or reset the counter on next prescaler clock 0x2 resync reload or reset the counter on next gen eric clock. reset the prescaler counter 0x3 - reserved
459 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 28-5. prescaler z bit 7 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 6:5 ? wavegen[1:0]: w aveform generation operation these bits select the waveform generation operation. they affect the top value, as shown in ?waveform output operations? on page 447 . it also controls whether frequency or pwm waveform generation should be used. how these modes differ can also be seen from ?waveform output operations? on page 447 . these bits are not synchronized. table 28-6. waveform generation operation note: 1. this depends on the tc mode. in 8-bit mode, the t op value is the period value register (per). in 16- and 32-bit mode it is the maximum value. z bit 4 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 3:2 ? mode[1:0]: tc mode these bits select the tc mode, as shown in table 28-7 . these bits are not synchronized. value name description 0x0 div1 prescaler: gclk_tc 0x1 div2 prescaler: gclk_tc/2 0x2 div4 prescaler: gclk_tc/4 0x3 div8 prescaler: gclk_tc/8 0x4 div16 prescaler: gclk_tc/16 0x5 div64 prescaler: gclk_tc/64 0x6 div256 prescaler: gclk_tc/256 0x7 div1024 prescaler: gclk_tc/1024 value name operation top value output waveform on match output waveform on wraparound 0x0 nfrq normal frequency per (1) /max to g g l e no action 0x1 mfrq match frequency cc0 to g g l e no action 0x2 npwm normal pwm per (1) /max set clear 0x3 mpwm match pwm cc0 set clear
460 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 28-7. tc mode z bit 1 ? enable: enable 0: the peripheral is disabled. 1: the peripheral is enabled. due to synchronization, there is delay from writing ctrla.enable until the peripheral is enabled/disabled. the value written to ctrla.enable will read back immediat ely, and the synchronization busy bit in the status regis- ter (status.syncbusy) will be set. status.syncbusy will be cleared when the operation is complete. z bit 0 ? swrst: software reset 0: there is no reset operation ongoing. 1: the reset operation is ongoing. writing a zero to this bit has no effect. writing a one to this bit resets all registers in the tc, except dbgctrl, to their initial state, and the tc will be disabled. writing a one to ctrla.swrst will always take precedence; all other writes in the same write-operation will be discarded. due to synchronization there is a delay from writing ctrla.swrst until the reset is complete. ctrla.swrst and status.syncbusy will both be cl eared when the reset is complete. value name description 0x0 count16 counter in 16-bit mode 0x1 count8 counter in 8-bit mode 0x2 count32 counter in 32-bit mode 0x3 - reserved
461 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.2 read request for a detailed description of this register and its use, refer to the ?synchronization? on page 452 . name: readreq offset: 0x02 reset: 0x0000 property: - z bit 15 ? rreq: read request writing a zero to this bit has no effect. this bit will always read as zero. writing a one to this bit requests synchronization of the register pointed to by the address bit group (read- req.addr) and sets the synchronization busy bit in the status register (status.syncbusy). z bit 14 ? rcont: read continuously 0: continuous synchronization is disabled. 1: continuous synchronization is enabled. when continuous synchronization is enabled, the register pointed to by the address bit group (readreq.addr) will be synchronized automatically every time the register is updated. z bits 13:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 4:0 ? addr[4:0]: address these bits select the offset of the register that needs read synchronization. in the tc, only count and ccx are available for read synchronization. bit151413121110 9 8 rreq rcont accesswr/wrrrrrr reset00000000 bit76543210 addr[4:0] access r r r r/w r/w r/w r/w r/w reset00000000
462 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.3 control b clear this register allows the user to change this register without doing a read-modify-write operation. changes in this register will also be reflected in the control b set (ctrlbset) register. name: ctrlbclr offset: 0x04 reset: 0x00 property: write-protected, write-synchronized, read-synchronized z bits 7:6 ? cmd[1:0]: command these bits are used for software control of retriggering and stopping the tc. when a command has been exe- cuted, the cmd bit group will read back as zero. the commands are executed on the next prescaled gclk_tc clock cycle. writing a zero to one of these bits has no effect. writing a one to one of these bits will clear the pending command. table 28-8. command z bits 5:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? oneshot: one-shot this bit controls one-shot operation of the tc. when in one-shot mode, the tc will stop counting on the next over- flow/underflow condition or a stop command. 0: the tc will wrap around and continue c ounting on an overflow/underflow condition. 1: the tc will wrap around and stop on the next underflow/overflow condition. writing a zero to this bit has no effect writing a one to this bit will disable one-shot operation. z bit 1 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 0 ? dir: counter direction this bit is used to change the direction of the counter. 0: the timer/counter is counting up (incrementing). bit76543210 cmd[1:0] oneshot dir access r/w r/w r r r r/w r r/w reset00000000 value name description 0x0 none no action 0x1 retrigger force a start, restart or retrigger 0x2 stop force a stop 0x3 - reserved
463 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 1: the timer/counter is c ounting down (decrementing). writing a zero to this bit has no effect. writing a one to this bit will make the counter count up.
464 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.4 control b set this register allows the user to change this register without doing a read-modify-write operation. changes in this register will also be reflected in the control b set (ctrlbclr) register. name: ctrlbset offset: 0x05 reset: 0x00 property: write-protected, write-synchronized, read-synchronized z bits 7:6 ? cmd[1:0]: command these bits is used for software control of retri ggering and stopping the tc. when a command has been executed, the cmd bit group will be read back as zero. the commands are executed on the next prescaled gclk_tc clock cycle. writing a zero to one of these bits has no effect. writing a one to one of these bits will set a command. table 28-9. command z bits 5:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? oneshot: one-shot this bit controls one-shot operation of the tc. when active, the tc will stop counting on the next overflow/under- flow condition or a stop command. 0: the tc will wrap around and continue c ounting on an overflow/underflow condition. 1: the timer/counter will wrap around and stop on the next underflow/overflow condition. writing a zero to this bit has no effect. writing a one to this bit will enable one-shot operation. z bit 1 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 0 ? dir: counter direction this bit is used to change the direction of the counter. 0: the timer/counter is counting up (incrementing). bit76543210 cmd[1:0] oneshot dir access r/w r/w r r r r/w r r/w reset00000000 value name description 0x0 none no action 0x1 retrigger force a start, restart or retrigger 0x2 stop force a stop 0x3 - reserved
465 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 1: the timer/counter is c ounting down (decrementing). writing a zero to this bit has no effect writing a one to this bit will make the counter count down.
466 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.5 control c name: ctrlc offset: 0x06 reset: 0x00 property: write-protected, write-synchronized, read-synchronized z bits 7:6 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 5:4 ? cptenx: capture channel x enable these bits are used to select whether channel x is a capture or a compare channel. writing a one to cptenx enables capture on channel x. writing a zero to cptenx disables capture on channel x. z bits 3:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 1:0 ? invenx: output waveform x invert enable these bits are used to select inversion on the output of channel x. writing a one to invenx inverts the output from wo[x]. writing a zero to invenx disables inversion of the output from wo[x]. bit76543210 cpten1 cpten0 inven1 inven0 access r r r/w r/w r r r/w r/w reset00000000
467 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.6 debug control name: dbgctrl offset: 0x08 reset: 0x00 property: write-protected z bits 7:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? dbgrun: debug run mode this bit is not affected by a software reset, and should not be changed by software while the tc is enabled. 0: the tc is halted when the device is halted in debug mode. 1: the tc continues normal operation when the device is halted in debug mode. bit76543210 dbgrun accessrrrrrrrr/w reset00000000
468 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.7 event control name: evctrl offset: 0x0a reset: 0x0000 property: write-protected, enable-protected z bits 15:14 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 13:12 ? mceox: match or capt ure channel x event output enable these bits control whether event match or capture on channel x is enabled or not and generated for every match or capture. 0: match/capture event on channel x is disabled and will not be generated. 1: match/capture event on channel x is enabled and will be generated for every compare/capture. these bits are not enable-protected. z bits 11:9 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 8 ? ovfeo: overflow/unde rflow event ou tput enable this bit is used to enable the overflow/underflow event. when enabled an event will be generated when the coun- ter overflows/underflows. 0: overflow/underflow event is disabled and will not be generated. 1: overflow/underflow event is enabled and will be generated for every counter overflow/underflow. this bit is not enable-protected. z bits 7:6 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 5 ? tcei: tc event input this bit is used to enable input events to the tc. 0: incoming events are disabled. 1: incoming events are enabled. this bit is not enable-protected. bit151413121110 9 8 mceo1 mceo0 ovfeo access r r r/w r/w r r r r/w reset00000000 bit76543210 tcei tcinv evact[2:0] access r r r/w r/w r r/w r/w r/w reset00000000
469 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bit 4 ? tcinv: tc inverted event input this bit inverts the input event source when used in pwp or ppw measurement. 0: input event source is not inverted. 1: input event source is inverted. this bit is not enable-protected. z bit 3 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 2:0 ? evact[2:0]: event action these bits define the event action the tc will perform on an event,as shown in table 28-10 . table 28-10. event action value name description 0x0 off event action disabled 0x1 retrigger start, restart or retrigger tc on event 0x2 count count on event 0x3 start start tc on event 0x4 - reserved 0x5 ppw period captured in cc0, pulse width in cc1 0x6 pwp period captured in cc1, pulse width in cc0 0x7 - reserved
470 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.8 interrupt enable clear this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable set register (intenset). name: intenclr offset: 0x0c reset: 0x00 property: write-protected z bits 7:6 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 5:4 ? mcx: match or capt ure channel x interrupt enable 0: the match or capture channel x interrupt is disabled. 1: the match or capture channel x interrupt is enabled. writing a zero to mcx has no effect. writing a one to mcx will clear the corresponding match or capture channel x interrupt disable/enable bit, which disables the match or capture channel x interrupt. z bit 3 ? syncrdy: synchronization ready interrupt enable 0: the synchronization ready interrupt is disabled. 1: the synchronization ready interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the synchronization read y interrupt disable/enable bit, which disables the syn- chronization ready interrupt. z bit 2 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 1 ? err: error interrupt enable 0: the error interrupt is disabled. 1: the error interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the error interrupt di sable/enable bit, which disables the compare interrupt. z bit 0 ? ovf: overflow interrupt enable 0: the overflow interrupt is disabled. 1: the overflow interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the overflow interrupt disable/enable bit, which disables the overflow interrupt. bit76543210 mc1 mc0 syncrdy err ovf access r r/w r/w r/w r/w r r/w r/w reset00000000
471 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.9 interrupt enable set this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear register (intenclr). name: intenset offset: 0x0d reset: 0x00 property: write-protected z bits 7:6 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 5:4 ? mcx: match or capt ure channel x interrupt enable 0: the match or capture channel x interrupt is disabled. 1: the match or capture channel x interrupt is enabled. writing a zero to mcx has no effect. writing a one to mcx will set the corresponding match or capture channel x interrupt enable bit, which enables the match or capture channel x interrupt. z bit 3 ? syncrdy: synchronization ready interrupt enable 0: the synchronization ready interrupt is disabled. 1: the synchronization ready interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the synchronization ready interrupt disable/enable bit, which enables the syn- chronization ready interrupt. z bit 2 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 1 ? err: error interrupt enable 0: the error interrupt is disabled. 1: the error interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the error interrupt bit, which enables the error interrupt. z bit 0 ? ovf: overflow interrupt enable 0: the overflow interrupt is disabled. 1: the overflow interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the overflow interrupt enable bit, which enables the overflow interrupt. bit76543210 mc1 mc0 syncrdy err ovf access r r r/w r/w r/w r r/w r/w reset00000000
472 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.10 interrupt flag status and clear name: intflag offset: 0x0e reset: 0x00 property: property: - z bits 7:6 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 5:4 ? mcx: match or capture channel x this flag is set on the next clk_tc_cnt cycle after a match with the compare condition or once ccx register contain a valid capture value, and will generate an interrupt request if the corresponding match or capture chan- nel x interrupt enable bit in the interrupt enable set register (intenset.mcx) is one. writing a zero to one of these bits has no effect. writing a one to one of these bits will clear the corresponding match or capture channel x interrupt flag in capture mode, this flag is automatically cl eared on the read of the ccx register by the cpu. z bit 3 ? syncrdy: synchronization ready this flag is set on a 1-to-0 transition of the synchroniza tion busy bit in the status register (status.syncbusy), except when the transition is caused by an enable or software reset, and will generate an interrupt request if the synchronization ready interrupt enable bit in the inte rrupt enable set register (intenset.syncrdy) is one. writing a zero to this bit has no effect. writing a one to this bit will clear the synchronization ready interrupt flag z bit 2 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bit 1 ? err: error this flag is set if a new capture occurs on a channel when the corresponding match or capture channel x interrupt flag is one, in which case there is nowhere to store the new capture. writing a zero to this bit has no effect. writing a one to this bit clears the error interrupt flag. z bit 0 ? ovf: overflow this flag is set on the next clk_tc_cnt cycle after an overflow condition occurs, and will generate an interrupt if intenclr/set.ovf is one. writing a zero to this bit has no effect. writing a one to this bit clears the overflow interrupt flag. bit76543210 mc1 mc0 syncrdy err ovf access r r r/w r/w r/w r r/w r/w reset00000000
473 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.11 status name: status offset: 0x0f reset: 0x08 property: property: - z bit 7 ? syncbusy: synchronization busy this bit is cleared when the synchronization of registers between the clock domains is complete. this bit is set when the synchronization of registers between clock domains is started. z bits 6:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 4 ? slave: slave this bit is set when the even-numbered master tc is se t to run in 32-bit mode. the odd-numbered tc will be the slave. z bit 3 ? stop: stop this bit is set when the tc is disabled, on a stop command or on an overflow or underflow condition when the one-shot bit in the control b set register (ctrlbset.oneshot) is one. 0: counter is running. 1: counter is stopped. z bits 2:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. bit76543210 syncbusy slave stop accessrrrrrrrr reset00001000
474 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.12 counter value 28.8.12.1 8-bit mode name: count offset: 0x10 reset: 0x00 property: write-synchronized, read-synchronized z bits 7:0 ? count[7:0]: counter value these bits contain the current counter value. bit76543210 count[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
475 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.12.2 16-bit mode name: count offset: 0x10 reset: 0x0000 property: write-synchronized, read-synchronized z bits 15:0 ? count[15:0]: counter value these bits contain the current counter value. bit151413121110 9 8 count[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 count[7:0] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000
476 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.12.3 32-bit mode name: count offset: 0x10 reset: 0x00000000 property: write-synchronized, read-synchronized z bits 31:0 ? count[31:0]: counter value these bits contain the current counter value. bit3130292827262524 count[31:24] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000 bit151413121110 9 8 count[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit2322212019181716 count[23:16] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 count[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
477 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.13 period value the period value register is available only in 8-bit tc mode. it is not available in 16-bit and 32-bit tc modes. 28.8.13.1 8-bit mode name: per offset: 0x14 reset: 0xff property: write-synchronized, read-synchronized z bits 7:0 ? per[7:0]: period value these bits contain the counter period value in 8-bittc mode. bit76543210 per[7:0] accessr/wr/wr/wr/wr/wr/wr/wr/w reset11111111
478 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.14 compare/capture 28.8.14.1 8-bit mode name: ccx offset: 0x18+i*0x1 [i=0..3] reset: 0x00 property: write-synchronized, read-synchronized z bits 7:0 ? cc[7:0]: compare/capture value these bits contain the compare/capture value in 8-bi t tc mode. in frequency or pwm waveform match operation (ctrla.wavegen), the cc0 register is used as a period register. bit76543210 cc[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
479 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.14.2 16-bit mode name: ccx offset: 0x18+i*0x2 [i=0..3] reset: 0x0000 property: write-synchronized, read-synchronized z bits 15:0 ? cc[15:0]: compare/capture value these bits contain the compare/capture value in 16-bi t tc mode. in frequency or pwm waveform match operation (ctrla.wavegen), the cc0 register is used as a period register. bit151413121110 9 8 cc[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 cc[7:0] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000
480 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.8.14.3 32-bit mode name: ccx offset: 0x18+i*0x4 [i=0..3] reset: 0x00000000 property: write-synchronized, read-synchronized z bits 31:0 ? cc[31:0]: compare/capture value these bits contain the compare/capture value in 32- bit tc mode. in frequency or pwm waveform match opera- tion (ctrla.wavegen), the cc0 regist er is used as a period register. bit3130292827262524 cc[31:24] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000 bit2322212019181716 cc[23:16] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit151413121110 9 8 cc[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 cc[7:0] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000
481 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29. adc ? analog-to-digital converter 29.1 overview the analog-to-digital converter (adc) converts analog signals to digital values. the adc has 12-bit resolution, and is capable of converting up to 350ksps. the input selection is flexible, and both differential and single-ended measurements can be performed. for differential measurements, an optional gain stage is available to increase the dynamic range. in addition, several internal signal inputs are avail able. the adc can provide both signed and unsigned results. adc measurements can be started by either application softwa re or an incoming event from another peripheral in the device. adc measurements can be started with predictable timing, and without software intervention. both internal and external reference voltages can be used. an integrated temperature sensor is available for use with the adc. the bandgap voltage as well as the scaled i/o and core voltages can also be measured by the adc. the adc has a compare function for accurate monitoring of user-defined thresholds, with minimum software intervention required. the adc may be configured for 8-, 10- or 12-bit results, reducing the conversion time. adc conversion results are provided left- or right-adjusted, which eases calcul ation when the result is represented as a signed value. 29.2 features z 8-, 10- or 12-bit resolution z up to 350,000 samples per second (ksps) z differential and single-ended inputs z up to 32 analog inputs z 25 positive and 10 negative, including internal and external z five internal inputs z bandgap z temperature sensor z dac z scaled core supply z scaled i/o supply z 1/2x to 16x gain z single, continuous and pin-scan conversion options z windowing monitor with selectable channel z conversion range: z v ref [1v to v ddana -0.6v] z adcx * gain [0v to -v ref ] z built-in internal reference and external reference options z four bits for reference selection
482 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z event-triggered conversion for accurate timing (one event input) z hardware gain and offset compensation z averaging and oversampling with decimation to support, up to 16-bit result z selectable sampling time 29.3 block diagram figure 29-1. adc block diagram 29.4 signal description note: 1. refer to ?configuration summary? on page 3 for details on exact number of analog input channels. refer to ?i/o multiplexing and considerations? on page 15 for details on the pin mapping for this peripheral. one signal can be mapped on several pins. adc adc0 adcn ... int.sig adc0 adcn int.sig ... refctrl int1v intvcc arefb offsetcorr gaincorr swtrig evctrl avgctrl winctrl sampctrl winut post processing prescaler ctrla winlt arefa ctrlb result inputctrl signal name type description arefa analog input external reference voltage a arefb analog input external reference voltage b adc[19..0] (1) analog input analog input channels
483 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 29.5.1 i/o lines using the adc's i/o lines requires the i/o pins to be configured using the port configuration (port). refer to ?port? on page 289 for details. 29.5.2 power management the adc will continue to operate in any sleep mode where the selected source clock is running. the adc?s interrupts can be used to wake up the device from sleep modes. the events can trigger other operations in the system without exiting the sleep modes. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. 29.5.3 clocks the adc bus clock (clk_adc_apb) can be enabled and dis abled in the power manager, and the default state of clk_adc_apb can be found in the table 16-1 . a generic clock (gclk_adc) is required to clock the adc. this clock must be configured and enabled in the generic clock controller (gclk) before using the adc. refer ?gclk ? generic clock controller? on page 83 for details. this generic clock is asynchronous to the bus clock (clk_a dc_apb). due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. refer to ?synchronization? on page 491 for further details. 29.5.4 dma not applicable. 29.5.5 interrupts the interrupt request line is connected to the interrupt controlle r. using adc interrupts requires the interrupt controller to be configured first. refer to ?nested vector interrupt controller? on page 28 for details. 29.5.6 events events are connected to the event system. refer to ?evsys ? event system? on page 314 for details. 29.5.7 debug operation when the cpu is halted in debug mode, the adc will halt normal operation. the adc can be forced to continue operation during debugging. refer to the debug control register (dbgctrl) for details. 29.5.8 register access protection all registers with write-access are optionally write-protected by the peripheral access controller (pac), except the following register: z interrupt flag status and clear register (intflag) write-protection is denoted by the write-protection property in the register description. when the cpu is halted in debug mode or the cpu reset is extended, all write-protection is automatically disabled. write-protection does not apply for accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details. 29.5.9 analog connections i/o-pins ain0 to ain15 as well as the arefa/arefb reference voltage pin are analog inputs to the adc.
484 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.5.10 calibration the values bias_cal and linearity_cal from the production test must be loaded from the nvm software calibration row into the adc calibration register (calib) by software to achieve specified accuracy. the gain and offset correction values from the production test can be loaded from the software calibration row into the gaincorr and offsetcorr registers by software to achieve specified accuracy. refer to ?nvm software calibration row mapping? on page 26 for more details. 29.6 functional description 29.6.1 principle of operation by default, the adc provides results with 12-bit resolution. 8- bit or 10-bit results can be selected in order to reduce the conversion time. the adc has an oversampling with decimation option that can extend the resolution to 16 bits. the input values can be either internal (e.g., internal temperatur e sensor) or external (connected i/o pins). the user can also configure whether the conversion should be single-ended or differential. 29.6.2 basic operation 29.6.2.1 initialization before enabling the adc, the asynchronous clock source must be selected and enabled, and the adc reference must be configured. the first conversion after the reference is changed must not be used. all other configuration registers must be stable during the conversion. the source for gclk_adc is selected and enabled in the system controller (sysctrl). refer to ?sysctrl ? system controller? on page 132 for more details. when gclk_adc is enabled, the adc can be enabled by writi ng a one to the enable bit in the control register a (ctrla.enable). 29.6.2.2 enabling, disabling and reset the adc is enabled by writing a one to the enable bit in t he control a register (ctrla.e nable). the adc is disabled by writing a zero to ctrla.enable. the adc is reset by writing a one to the software reset bit in the control a register (ctrla.s wrst). all registers in the adc, except dbgctrl, will be reset to their initial state, and the adc will be disabled. refer to the ctrla register for details. the adc must be disabled before it is reset. 29.6.2.3 basic operation in the most basic configuration, the adc sample values fr om the configured internal or external sources (inputctrl register). the rate of the conversion is dependent on the combination of the gclk_adc frequency and the clock prescaler. to convert analog values to digital values, the adc needs first to be initialized, as described in ?initialization? on page 484 . data conversion can started either manually, by writing a one to the start bit in the software trigger register (swtrig.start), or automatically, by c onfiguring an automatic trigger to initia te the conversions. a free-running mode could be used to continuously convert an input channel. there is no need for a trigger to start the conversion. it will start automatically at the end of previous conversion. the automatic trigger can be configured to trigger on many different conditions. the result of the conversion is stored in the result register (r esult) as it becomes available, overwriting the result from the previous conversion. to avoid data loss if more than one channel is enabled, the conversion result must be read as it becomes available (intflag.resrdy). failing to do so will result in an overr un error condition, indicated by the overrun bit in the interrupt flag status and clear register (intflag.overrun).
485 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 to use an interrupt handler, the corresponding bit in the inte rrupt enable set register (int enset) must be written to one. 29.6.3 prescaler the adc is clocked by gclk_adc. there is also a prescale r in the adc to enable conversion at lower clock rates. . refer to for details on prescaler settings. figure 29-2. adc prescaler the propagation delay of an adc measurement is given by: 29.6.4 adc resolution the adc supports 8-bit, 10-bit and 12-bit resolutions. resolu tion can be changed by writing the resolution bit group in the control b register (ctrlb.ressel). after a reset, the resolution is set to 12 bits by default. table 29-1. delay gain intputctrl.gain[3:0] delay gain (in clk_adc period) differential mode single-ended mode 0x0 0 0 0x1 0 1 0x2 1 1 0x3 1 2 0x4 2 2 0x5 ... 0xe reserved reserved 0xf 0 1 gclk_adc 9-bit prescaler ctrlb.prescaler[2:0] div512 div256 div128 div64 div32 div16 div8 div4 clk_adc propagationdelay 1 resolution 2 ---------------------------- delaygain ++ f adc ------------------------------------------------------------------------- - =
486 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.6.5 differential and single-ended conversions the adc has two conversion options: differential and single- ended. when measuring signals where the positive input is always at a higher voltage than the negative input, the single-ended conversion should be used in order to have full 12- bit resolution in the conversion, which has only positive values. the negative input must be connected to ground. this ground could be the internal gnd, iognd or an external ground connected to a pin. refer to for selection details. if the positive input may go below the negative input, creating some negative results, the differential mode should be used in order to get correct results. the configuration of the c onversion is done in the differential mode bit in the control b register (ctrlb.diffmode). these two types of conversion could be run in si ngle mode or in free-running mode. when set up in free-running mode, an adc input will continuously sample and do new conversions. the intflag.resrdy bit will be set at the end of each conversion. 29.6.5.1 conversion timing figure 29-3 shows the adc timing for a single conversion without gain. the writing of the adc start conversion bit (swtrig.start) or start conversion event in bit (evctr l.startei) must occur at least one clk_adc_apb cycle before the clk_adc cycle on which the conversion starts. the input channel is sampled in the first half clk_adc period. the sampling time can be increased by using the sa mpling time length bit group in the sampling time control register (sampctrl.samplen). refer to figure 29-4 for example on increased sampling time. figure 29-3. adc timing for one conversi on in differential mode without gain figure 29-4. adc timing for one conver sion in differential mode without ga in, but with incre ased sampling time 12345678 clk_ adc start sample int converting bit msb10987654321lsb 12345678 clk_ adc start sample int converting bit msb10987654321lsb 91011
487 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 29-5. adc timing for free runni ng in differential mode without gain figure 29-6. adc timing for one conversi on in single-ended mode without gain figure 29-7. adc timing for free runni ng in single-ended mode without gain 1 2345678 clk_ adc start sample int converting bit 91011 12 13 14 15 16 11109876543210 11 1098765432101110 98765 12345678 clk_ adc start sample int conver ting bit 91011 amplify msb10987654321lsb 1 2345678 clk_ adc start sample int converting bit 91011 12 13 14 15 16 11109876543210 11 109876543210 1110 amplify
488 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.6.6 averaging averaging is a feature that increases the sample accuracy, though at the cost of reduced sample rate. if enabled, the adc automatically computes an average value of multiple consecutive conversions. this feature is suitable when operating in noisy conditions.the number of samples to be av eraged is specified by the number of samples to be collected bit group in the average control register (avgct rl.samplenum[3:0]), and the averaged output is available in the result register (result). table 29-2 specifies the number of samples that will be accumulated. when averaging by the number of samples to be collected bit group in the average control register (avgctrl.samplenum[3:0]), the effective adc sample rate is reduced by that factor. when the required average is reached, the intflag.resrdy bit is set. table 29-2. averaging 29.6.7 oversampling and decimation in oversampling and decimation, the adc resolution is increased from 12 bits to the programmed 13, 14, 15 or 16 bits. if the resolution is to be increased by n bits, 4 n samples are accumulated, and the result is right shifted by the number of bits specified in the adjusting result/division coefficient bit group in the average control register (avctrl.adjres[2:0]). this method will result in n-bit extra lsb resolution. table 29-3. configuration required for oversampling and decimation avgctrl.samplenum[3:0] number of samples final result precision ctrlb.ressel[1:0] factor reduction 0x0 1 12 bits 0x0 0 0x1 2 13 bits 0x1 0 0x2 4 14 bits 0x1 0 0x3 8 15 bits 0x1 0 0x4 16 16 bits 0x1 0 0x5 32 16 bits 0x1 2 0x6 64 16 bits 0x1 4 0x7 128 16 bits 0x1 8 0x8 256 16 bits 0x1 16 0x9 512 16 bits 0x1 32 0xa 1024 16 bits 0x1 64 0xb ?0xf reserved 12 bits 0x0 0 increase resolution by number of samples to average avgctrl.samplenum[3:0] avgctrl.adjres[2:0] final result precision 1 bit 4 1 = 4 0x2 0x1 13 bits 2 bits 4 2 = 16 0x4 0x2 14 bits 3 bits 4 3 = 64 0x6 0x3 15 bits 4 bits 4 4 = 256 0x8 0x4 16 bits
489 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.6.8 window monitor the window monitor allows the conversion result to be compared to some predefined threshold values. supported modes are selected by writing the window monitor m ode bit group in the window monitor control register (winctrl.winmode[2:0]). thresholds are given by writing the window monitor lower threshold register (winlt) and window monitor upper thre shold register (winut). if differential input is selected, the winlt and winut are evaluated as signed values. otherwise they are evaluated as unsigned values. another important point is that the significant winlt and winut bits are given by the precision selected in the conversion result resolution bit group in the control b regi ster (ctrlb.ressel). this means that if 8-bit mode is selected, only the eight lower bits will be considered. in additi on, in differential mode, the eighth bit will be considered as the sign bit even if the ninth bit is zero. the intflag.winmon interrupt flag will be set if the c onversion result matches the window monitor condition. 29.6.9 offset and gain correction inherent gain and offset errors affect the absolute accuracy of the adc. the offset error is defined as the deviation of the actual adc?s transfer function from an ideal straight line at zero input voltage. the offset error cancellation is handled by the offset correction register (offsetcorr). the offset co rrection value is subtracted from the converted data before writing the result register (result). t he gain error is defined as the deviation of the last output step?s midpoint from the ideal straight line, after compensating for offset error. the gain error cancellation is handled by the gain correction register (gaincorr). to correct these two errors, the digi tal correction logic enabled bit in the control b register (ctrlb.corren) must be written to one. offset and gain error compensation results are both calculated according to: in single conversion, a latency of 13 gclk_adc is added to the av ailability of the final result. since the correction time is always less than the propagation delay, this latency appears in free-running mode only during the first conversion. after that, a new conversion will be initialized when a conversion co mpletes. all other conversion results are available at the defined sampling rate. figure 29-8. adc timing correction enabled result conversion value offsetcorr ? () gaincorr ? = start conv0 conv1 conv2 conv3 corr0 corr1 corr2 corr3
490 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.6.10 additional features 29.6.10.1 synchronization due to the asynchronicity between clk_adc_apb and gc lk_adc, some registers must be synchronized when accessed. a register can require: z synchronization when written z synchronization when read z synchronization when written and read z no synchronization when executing an operation that requires synchronization, the synchronization busy bit in the status register (status.syncbusy) will be set immediately, and cleared when synchronization is complete. the synchronization ready interrupt can be used to signal w hen synchronization is complete. this can be accessed via the synchronization ready interrupt flag in the interrupt flag status and clear register (intflag.syncrdy). if an operation that requires synchronization is executed wh ile status.syncbusy is one, the bus will be stalled. all operations will complete successfully, but the cpu will be stalled and interrupts will be pending as long as the bus is stalled. the following bits need synchronization when written: z software reset bit in the control a register (ctrla.swrst) z enable bit in the control a register (ctrla.enable) write-synchronization is denoted by the write-synchronized property in the register description. the following bits need synchronization when read: z all bits in the count register (count) z prescaler bit in the control a register (ctrla.prescaler) read-synchronization is denoted by the read-synchronized property in the register description. 29.6.11 interrupts the adc has the following interrupt sources: z result conversion ready: resrdy z overrun: overrun z window monitor: winmon z synchronization ready: syncrdy each interrupt source has an interrupt flag associated with i t. the interrupt flag in the interrupt flag status and clear register (intflag) is set when the interrupt condition occu rs. each interrupt can be individually enabled by writing a one to the corresponding bit in the interrupt enable set regi ster (intenset), and disabled by writing a one to the corresponding bit in the interrupt enable clear register (int enclr) register. an interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset. an interrupt flag is cleared by writing a one to the corresponding bit in the intflag register. each peripheral can have one interrupt request line per interrupt source or one common interrupt request line for all the interrupt sources. this is device dependent. refer to ?nested vector interrupt controller? on page 28 for details. if the peripheral has one common interrupt request line for all the interrupt sources, the user must read the intflag register to determine which interrupt condition is present. 29.6.12 events the peripheral can generate the following output events: z result ready (resrdy)
491 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z window monitor (winmon) output events must be enabled to be generated. writing a one to an event output bit in the event control register (evctrl.xxeo) enables the corresponding output event. writing a zero to this bit disables the corresponding output event. the events must be correctly routed in the event system. refer to ?evsys ? event system? on page 314 for details. the peripheral can take the following actions on an input event: z adc start conversion (start) z adc conversion flush (flush) input events must be enabled for the corresponding action to be taken on any input event. writing a one to an event input bit in the event control register (evctrl.xxei) enabl es the corresponding action on the input event. writing a zero to this bit disables the corresponding action on the input event. note that if several events are connected to the peripheral, the enabled action will be taken on any of the inco ming events. the events must be correctly routed in the event system. refer to ?evsys ? event system? on page 314 for details. 29.6.13 sleep mode operation the run in standby bit in the control a register (ctrla .runstdby) controls the behavior of the adc during standby sleep mode. when the bit is zero, the adc is disabled during sleep, but maintains its current configuration. when the bit is one, the adc continues to operate during sleep. note that when runstdby is zero, the analog blocks are powered off for the lowest power consumption. this necessitates a start-up time delay when the system returns from sleep. when runstdby is one, any enabled adc interrupt source can wake up the cpu. however, adc conversion will be triggerable by events only while the cpu is idle. 29.6.14 synchronization due to the asynchronicity between clk_adc_apb and gc lk_adc, some registers must be synchronized when accessed. a register can require: z synchronization when written z synchronization when read z synchronization when written and read z no synchronization when executing an operation that requires synchronization, the synchronization busy bit in the status register (status.syncbusy) will be set immediately, and cleared when synchronization is complete. the synchronization ready interrupt can be used to signal when synchronization is complete. if an operation that requires synchronization is executed wh ile status.syncbusy is one, the bus will be stalled. all operations will complete successfully, but the cpu will be stalled and interrupts will be pending as long as the bus is stalled. the following bits need synchronization when written: z software reset bit in the control a register (ctrla.swrst) z enable bit in the control a register (ctrla.enable) the following registers need synchronization when written: z control b (ctrlb) z software trigger (swtrig) z window monitor control (winctrl) z input control (inputctrl) z window upper/lower threshold (winut/winlt) write-synchronization is denoted by the write-synchronized property in the register description. the following registers need synchronization when read:
492 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z software trigger (swtrig) z input control (inputctrl) z result (result) read-synchronization is denoted by the read-synchronized property in the register description.
493 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.7 register summary offset name bit pos. 0x00 ctrla 7:0 runstdby enable swrst 0x01 refctrl 7:0 refcomp refsel[3:0] 0x02 avgctrl 7:0 adjres[2:0] samplenum[3:0] 0x03 sampctrl 7:0 samplen[5:0] 0x04 ctrlb 7:0 ressel[1:0] corren freerun leftadj diffmode 0x05 15:8 prescaler[2:0] 0x06 reserved 0x07 reserved 0x08 winctrl 7:0 winmode[2:0] 0x09 reserved 0x0a reserved 0x0b reserved 0x0c swtrig 7:0 start flush 0x0d reserved 0x0e reserved 0x0f reserved 0x10 inputctrl 7:0 muxpos[4:0] 0x11 15:8 muxneg[4:0] 0x12 23:16 inputoffset[3:0] inputscan[3:0] 0x13 31:24 gain[3:0] 0x14 evctrl 7:0 winmoneo resrdyeo syncei startei 0x15 reserved 0x16 intenclr 7:0 syncrdy winmon overrun resrdy 0x17 intenset 7:0 syncrdy winmon overrun resrdy 0x18 intflag 7:0 syncrdy winmon overrun resrdy 0x19 status 7:0 syncbusy 0x1a result 7:0 result[7:0] 0x1b 15:8 result[15:8] 0x1c winlt 7:0 winlt[7:0] 0x1d 15:8 winlt[15:8] 0x1e reserved 0x1f reserved 0x20 winut 7:0 winut[7:0] 0x21 15:8 winut[15:8] 0x22 reserved 0x23 reserved
494 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 0x24 gaincorr 7:0 gaincorr[7:0] 0x25 15:8 gaincorr[11:8] 0x26 offsetcorr 7:0 offsetcorr[7:0] 0x27 15:8 offsetcorr[11:8] 0x28 calib 7:0 linearity_cal[7:0] 0x29 15:8 bias_cal[2:0] 0x2a dbgctrl 7:0 dbgrun offset name bit pos.
495 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each individual register description. refer to ?register access protection? on page 483 for details. some registers require synchronization when read and/or wr itten. synchronization is denoted by the write-synchronized or the read-synchronized property in each individual register description. refer to ?synchronization? on page 491 for details. some registers are enable-protected, meaning they can be wr itten only when the adc is disabled. enable-protection is denoted by the enable-protected property in each individual register description. 29.8.1 control a name: ctrla offset: 0x00 reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? runstdby: run in standby this bit indicates whether the adc willcontinue running in standby sleep mode or not: 0: the adc is halted during standby sleep mode. 1: the adc continues normal operation during standby sleep mode. z bit 1 ? enable: enable 0: the adc is disabled. 1: the adc is enabled. due to synchronization, there is a del ay from writing ctrla.enable until the peripheral is enabled/disabled. the value written to ctrl.enable will read back immediately and the synchronization busy bit in the status register (status.syncbusy) will be set. status.syncbusy will be cleared when the operation is complete. z bit 0 ? swrst: software reset 0: there is no reset operation ongoing. 1: the reset operation is ongoing. writing a zero to this bit has no effect. writing a one to this bit resets all registers in the adc, except dbgctrl, to their initial state, and the adc will be disabled. bit 76543210 runstdby enable swrst accessrrrrrr/wr/wr/w reset00000000
496 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 writing a one to ctrl.swrst will always take precedence, meaning that all other writes in the same write-oper- ation will be discarded. due to synchronization, there is a delay from writing ctrla.swrst until the reset is complete. ctrla.swrst and status.syncbusy will both be cl eared when the reset is complete.
497 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.2 reference control name: refctrl offset: 0x01 reset: 0x00 property: write-protected z bit 7 ? refcomp: reference buff er offset compensation enable the accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. this will decrease the input impedance and thus increase the start-up time of the reference. 0: reference buffer offset compensation is disabled. 1: reference buffer offset compensation is enabled. z bits 6:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 3:0 ? refsel[3:0]: reference selection these bits select the reference for the adc according to table 29-4 . table 29-4. reference selection bit 76543210 refcomp refsel[3:0] access r/w r r r r/w r/w r/w r/w reset00000000 value name description 0x0 int1v 1.0v voltage reference 0x1 intvcc0 1/1.48 vddana 0x2 intvcc1 1/2 vddana (only for vddana > 2.0v) 0x3 arefa external reference 0x4 arefb external reference 0x5-0xf reserved reserved
498 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.3 average control name: avgctrl offset: 0x02 reset: 0x00 property: write-protected z bit 7 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 6:4 ? adjres[2:0]: adjustin g result / division coefficient these bits define the division coefficient in 2 n steps. z bits 3:0 ? samplenum[3:0]: number of samples to be collected these bits define how many samples should be added together.the result will be available in the result register (result). note: if the result width increases, ctrlb.ressel must be changed. table 29-5. number of samples to be collected bit 76543210 adjres[2:0] samplenum[3:0] access r r/w r/w r/w r/w r/w r/w r/w reset00000000 value name description 0x0 1 sample 0x1 2 samples 0x2 4 samples 0x3 8 samples 0x4 16 samples 0x5 32 samples 0x6 64 samples 0x7 128 samples 0x8 256 samples 0x9 512 samples 0xa 1024 samples 0xb-0xf reserved
499 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.4 sampling time control name: sampctrl offset: 0x03 reset: 0x00 property: write-protected z bits 7:6 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 5:0 ? samplen[5:0]: sampling time length these bits control the adc sampling time in number of half clk_adc cycles, depending of the prescaler value, thus controlling the adc input impedance. sampling time is set according to the equation: bit 76543210 samplen[5:0] accessr r r/wr/wr/wr/wr/wr/w reset00000000 sampling time samplen 1 + () clk adc 2 ---------------------- ?? ?? ? =
500 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.5 control b name: ctrlb offset: 0x04 reset: 0x0000 property: write-synchronized, write-protected z bits 15:11 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 10:8 ? prescaler[2:0]: prescaler configuration these bits define the adc clock relative to the peripheral clock according to table 29-6 . these bits can only be written while the adc is disabled. table 29-6. prescaler configuration z bits 7:6 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 5:4 ? ressel[1:0]: co nversion result resolution these bits define whether the adc completes the conversion at 12-, 10- or 8-bit result resolution. these bits can be written only while the adc is disabled. bit 151413121110 9 8 prescaler[2:0] accessrrrrrr/wr/wr/w reset00000000 bit76543210 ressel[1:0] corren freerun leftadj diffmode access r r r/w r/w r/w r/w r/w r/w reset00000000 value name description 0x0 div4 peripheral clock divided by 4 0x1 div8 peripheral clock divided by 8 0x2 div16 peripheral clock divided by 16 0x3 div32 peripheral clock divided by 32 0x4 div64 peripheral clock divided by 64 0x5 div128 peripheral clock divided by 128 0x6 div256 peripheral clock divided by 256 0x7 div512 peripheral clock divided by 512
501 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 29-7. conversion result resolution z bit 3 ? corren: digital correction logic enabled 0: disable the digital result correction. 1: enable the digital result correction. the adc conversion re sult in the result register is then corrected for gain and offset based on the values in the gaincal and offs etcal registers. conversion time will be increased by x cycles according to the value in the offset correcti oin value bit group in the offset correction register. this bit can be changed only while the adc is disabled. z bit 2 ? freerun: free running mode 0: the adc run is single conversion mode. 1: the adc is in free running mode and a new conversion wi ll be initiated when a previous conversion completes. this bit can be changed only while the adc is disabled. z bit 1 ? leftadj: left adjusted result 0: the adc convertion result is right-adjusted in the result register. 1: the adc conversion result is left-adjusted in the result register. the high byte of the 12-bit result will be present in the upper part of the result register. writing this bit to zero (default) will right-adjust the value in the result register. this bit can be changed only while the adc is disabled. z bit 0 ? diffmode: differential mode 0: the adc is running in singled-ended mode. 1: the adc is running in differential mode. in this mode, the voltage difference between the muxpos and mux- neg inputs will be converted by the adc. this bit can be changed only while the adc is disabled. value name description 0x0 12bit 12-bit result 0x1 16bit for averaging mode output 0x2 10bit 10-bit result 0x3 8bit 8-bit result
502 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.6 window monitor control name: winctrl offset: 0x08 reset: 0x00 property: write-synchronized, write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 2:0 ? winmode[2:0]: window monitor mode these bits enable and define the window monitor mode. table 29-8 shows the mode selections. table 29-8. window monitor mode bit 76543210 winmode[2:0] accessrrrrrr/wr/wr/w reset00000000 value name description 0x0 no window mode (default) 0x1 mode 1: result > winlt 0x2 mode 2: result < winut 0x3 mode 3: winlt < result < winut 0x4 mode 4: !(winlt < result < winut) 0x5-0x7 reserved
503 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.7 software trigger name: swtrig offset: 0x0c reset: 0x00 property: write-synchronized, write-protected z bits 7:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? start: adc start conversion 0: the adc will not start a conversion. 1: the adc will start a conversion. the bit is cleared by hardware when the conversion has started. setting this bit when it is already set has no effect. writing this bit to zero will have no effect. z bit 0 ? flush: adc conversion flush 0: no flush action. 1: the adc pipeline will be flushed. a flush will restar t the adc clock on the next peripheral clock edge, and all conversions in progress will be aborted and lost. this bit is cleared until the adc has been flushed. after the flush, the adc will resume where it left off; i.e., if a conversion was pending, the adc will start a new conversion. writing this bit to zero will have no effect. bit76543210 start flush accessrrrrrrr/wr/w reset00000000
504 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.8 input control name: inputctrl offset: 0x10 reset: 0x00000000 property: write-synchronized, write-protected z bits 31:28 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 27:24 ? gain[3:0]: gain factor selection bit3130292827262524 gain[3:0] accessrrrrr/wr/wr/wr/w reset00000000 bit2322212019181716 inputoffset[3:0] inputscan[3:0] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000 bit151413121110 9 8 muxneg[4:0] access r r r r/w r/w r/w r/w r/w reset00000000 bit76543210 muxpos[4:0] access r r r r/w r/w r/w r/w r/w reset00000000
505 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 these bits set the gain factor of the adc gain stage according to the values shown in . z bits 23:20 ? inputoffset[3:0] : positive mux setting offset the pin scan is enabled when inputscan != 0. writing these bits to a value other than zero causes the first con- version triggered to be converted using a positive input equalto muxpos + inputoffset. setting this register to zero causes the first conversion to use a positive input equal to muxpos. after a conversion, the inputoffset register will be incremented by one, causing the next conversion to be done with the positive inputequal to muxpos + inputo ffset. the sum of muxpos and inputoffset gives the input that is actually converted. z bits 19:16 ? inputscan[3:0]: number of input channels included in scan this register gives the number of input sources included in the pin scan. the number of input sources included is inputscan + 1. the input channels included are in t he range from muxpos + in putoffset to muxpos + inputoffset + inputscan. the range of the scan mode must not exceded the number of input channels available on the device. z bits 15:13 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 12:8 ? muxneg[4:0]: negative mux input selection table 29-9. gain factor selection value name description 0x0 1x 1x 0x1 2x 2x 0x2 4x 4x 0x3 8x 8x 0x4 16x 16x 0x5-0xe ? reserved 0xf div2 1/2x
506 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 these bits define the mux selection for the negative adc input. table 29-10 shows the possible input selections. z bits 7:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 4:0 ? muxpos[4:0]: positive mux input selection these bits define the mux selection for the positive adc input. table 29-11 shows the possible input selections. ifthe internal bandgapvoltage or temperature sensor input channel is selected, thenthe sampling time length bit group in the samplingcontrol register must be written with a corresponding value. table 29-10. negative mux input selection value name description 0x00 pin0 adc ain0 pin 0x01 pin1 adc ain1 pin 0x02 pin2 adc ain2 pin 0x03 pin3 adc ain3 pin 0x04 pin4 adc ain4 pin 0x05 pin5 adc ain5 pin 0x06 pin6 adc ain6 pin 0x07 pin7 adc ain7 pin 0x08-0x17 ? reserved 0x18 gnd internal ground 0x19 iognd i/o ground 0x1a-0x1f ? reserved table 29-11. positive mux input selection muxpos[4:0] group configuration description 0x00 pin0 adc ain0 pin 0x01 pin1 adc ain1 pin 0x02 pin2 adc ain2 pin 0x03 pin3 adc ain3 pin 0x04 pin4 adc ain4 pin 0x05 pin5 adc ain5 pin 0x06 pin6 adc ain6 pin 0x07 pin7 adc ain7 pin 0x08 pin8 adc ain8 pin 0x09 pin9 adc ain9 pin 0x0a pin10 adc ain10 pin
507 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 0x0b pin11 adc ain11 pin 0x0c pin12 adc ain12 pin 0x0d pin13 adc ain13 pin 0x0e pin14 adc ain14 pin 0x0f pin15 adc ain15 pin 0x10 pin16 adc ain16 pin 0x11 pin17 adc ain17 pin 0x12 pin18 adc ain18 pin 0x13 pin19 adc ain19 pin 0x14-0x17 reserved 0x18 temp temperature peference 0x19 bandgap bandgap voltage 0x1a scaledcorevcc 1/4 scaled core supply 0x1b scalediovcc 1/4 scaled i/o supply 0x1c dac dac output 0x1d-0x1f reserved table 29-11. positive mux input selection (continued) muxpos[4:0] group configuration description
508 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.9 event control name: evctrl offset: 0x14 reset: 0x00 property: write-protected z bits 7:6 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 5 ? winmoneo: window monitor event out this bit indicates whether the window monitor event ouputt is enabled or not and an output event will be gener- ated when the window monitor detects something. 0: window monitor event output is disabled and an event will not be generated. 1: window monitor event output is enabled and an event will be generated. z bit 4 ? resrdyeo: result ready event out this bit indicates whether the result ready event output is enabled or not and an output event will be generated when the conversion result is available. 0: result ready eventoutputis disabled and an event will not be generated. 1: result ready event output is enabled and an event will be generated. z bits 3:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? syncei: synchronization event in 0: a flush and new conversion will not be triggered on any incoming event. 1: a flush and new conversion will be triggered on any incoming event. z bit 0 ? startei: start conversion event in 0: a new conversion will not be triggered on any incoming event. 1: a new conversion will be triggered on any incoming event. bit76 5 43210 winmoneo resrdyeo syncei startei access r r r/w r/w r r r/w r/w reset00 0 00000
509 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.10 interrupt enable clear this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable set register (intenset). name: intenclr offset: 0x16 reset: 0x00 property: write-protected z bits 7:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 3 ? syncrdy: synchronization ready interrupt enable 0: the synchronization ready interrupt is disabled. 1: the synchronization ready interrupt is enabled, and an interrupt request will be generated when the synchroni- zation ready interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the synchronization ready interrupt enable bit and the corresponding interrupt request. z bit 2 ? winmon: window monitor interrupt enable 0: the window monitor interrupt is disabled. 1: the window monitor interrupt is enabled, and an interrupt request will be generated when the window monitor interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the window monitor in terrupt enable bit and the corresponding interrupt request. z bit 1 ? overrun: overrun interrupt enable 0: the overrun interrupt is disabled. 1: the overrun interrupt is enabled, and an interrupt request will be generated when the overrun interrupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the overrun interrupt enable bit and the corresponding interrupt request. z bit 0 ? resrdy: result ready interrupt enable 0: the result ready interrupt is disabled. 1: the result ready interrupt is enabled, and an interrupt request will be generated when the result ready inter- rupt flag is set. writing a zero to this bit has no effect. writing a one to this bit will clear the result ready interrupt enable bit and the corresponding interrupt request. bit76543210 syncrdy winmon overrun resrdy access r r r r r/w r/w r/w r/w reset00000000
510 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.11 interrupt enable set this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear register (intenclr). name: intenset offset: 0x17 reset: 0x00 property: write-protected z bits 7:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 3 ? syncrdy: synchronization ready interrupt enable 0: the synchronization ready interrupt is disabled. 1: the synchronization ready interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the synchronization ready interrupt enable bit, which enables the synchronization ready interrupt. z bit 2 ? winmon: window monitor interrupt enable 0: the window monitor interrupt is disabled. 1: the window monitor interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the window monitor interrupt bit and enable the window monitor interrupt. z bit 1 ? overrun: overrun interrupt enable 0: the overrun interrupt is disabled. 1: the overrun interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the overrun interrupt bit and enable the overrun interrupt. z bit 0 ? resrdy: result ready interrupt enable 0: the result ready interrupt is disabled. 1: the result ready interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the result ready interrupt bit and enable the result ready interrupt. bit76543210 syncrdy winmon overrun resrdy access r r r r r/w r/w r/w r/w reset00000000
511 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.12 interrupt flag status and clear name: intflag offset: 0x18 reset: 0x00 property: ? z bits 7:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 3 ? syncrdy: synchronization ready this flag is cleared by writing a one to the flag. this flag is set on a one-to-zero transition of the synchr onization busy bit in the status register (status.sync- busy), except when caused by an enable or software reset, and will generate an interrupt request if intenclr/set.syncrdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the synchronization ready interrupt flag. z bit 2 ? winmon: window monitor this flag is cleared by writing a one to the flag. this flag is set on the next gclk_adc cycle after a match with the window monitor condition, and an interrupt request will be generated if intenclr/set.winmon is one. writing a zero to this bit has no effect. writing a one to this bit clears the window monitor interrupt flag. z bit 1 ? overrun: overrun this flag is cleared by writing a one to the flag. this flag is set if result is written before the prev ious value has been read by cpu, and an interrupt request will be generated if intenclr/set.overrun is one. writing a zero to this bit has no effect. writing a one to this bit clears the overrun interrupt flag. z bit 0 ? resrdy: result ready this flag is cleared by writing a one to the flag. this flag is set when the conversion result is available, and an interrupt will be generated if inten- clr/set.resrdy is one. writing a zero to this bit has no effect. writing a one to this bit clears the result ready interrupt flag. bit76543210 syncrdy winmon overrun resrdy access r r r r r/w r/w r/w r/w reset00000000
512 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.13 status name: status offset: 0x19 reset: 0x00 property: ? z bit 7 ? syncbusy: synchronization busy this bit is cleared when the synchronization of registers between the clock domains is complete. this bit is set when the synchronization of registers between clock domains is started. z bits 6:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. bit76543210 syncbusy accessrrrrrrrr reset00000000
513 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.14 result name: result offset: 0x1a reset: 0x0000 property: read-synchronized z bits 15:0 ? result[15:0]: result conversion value these bits will hold up to a 16-bit adc result, depending on the configuration. in single-ended without averaging mode, the adc conversion will produce a 12-bit result, which can be left- or right-shifted, depending on the setting of ctrlb.leftadj. if the result is left-adjusted (ctrlb.leftadj), the high byte of the result will be in bit position [15:8], while the remaining 4 bits of the result will be placed in bit locations [7:4]. this can be used only if an 8-bit result is required; i.e., one can read only the high byte of the entire 16-bit register. if the result is not left-adjusted (c trlb.leftadj) and no oversampling is used, the result will be available in bit locations [11:0], and the result is then 12 bits long. if oversampling is used, the result will be located in bit locations [15:0], depending on the settings of the average control register ( avgctrl ). bit151413121110 9 8 result[15:8] accessrrrrrrrr reset00000000 bit76543210 result[7:0] accessrrrrrrrr reset00000000
514 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.15 window monitor lower threshold name: winlt offset: 0x1c reset: 0x0000 property: write-synchronized, write-protected z bits 15:0 ? winlt[15:0]: window lower threshold if the window monitor is enabled, these bits define the lower threshold value. bit151413121110 9 8 winlt[15:8] acces s r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 winlt[7:0] acces s r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
515 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.16 window monitor upper threshold name: winut offset: 0x20 reset: 0x0000 property: write-synchronized, write-protected z bits 15:0 ? winut[15:0]: window upper threshold if the window monitor is enabled, these bits define the upper threshold value. bit151413121110 9 8 winut[15:8] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 winut[7:0] accessr/wr/wr/wr/wr/wr/wr/wr/w reset00000000
516 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.17 gain correction name: gaincorr offset: 0x24 reset: 0x0000 property: write-protected z bits 15:12 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 11:0 ? gaincorr[11:0]: gain correction value if the ctrlb.corren bit is one, these bits define how the adc conversion result is compensated for gain error before being written to the result register. the gaincorrectio n is a fractional value, a 1-bit integer plusan 11-bit frac- tion, and therefore ? <= gaincorr < 2. gaincorr values range from 0.10000000000 to 1.11111111111. bit151413121110 9 8 gaincorr[11:8] accessrrrrr/wr/wr/wr/w reset00000000 bit76543210 gaincorr[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
517 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.18 offset correction name: offsetcorr offset: 0x26 reset: 0x0000 property: write-protected z bits 15:12 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 11:0 ? offsetcorr[11:0]: offset correction value if the ctrlb.corren bit is one, these bits define how t he adc conversion result is compensated for offset error before being written to the result register. this offsetcorr value is in two?s complement format. bit151413121110 9 8 offsetcorr[11:8] access r r r r r/w r/w r/w r/w reset00000000 bit76543210 offsetcorr[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
518 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.19 calibration name: calib offset: 0x28 reset: 0x0000 property: write-protected z bits 15:11 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 10:8 ? bias_cal[2:0]: bias calibration value this value from production test must be loaded from the nvm software calibration row into the calib register by software to achieve the specified accuracy. thevalue must be copied only, and must not be changed. z bits 7:0 ? linearity_cal[7:0] : linearity calibration value this value from production test must be loaded from the nvm software calibration row into the calib register by software to achieve the specified accuracy. thevalue must be copied only, and must not be changed. bit151413121110 9 8 bias_cal[2:0] accessrrrrrr/wr/wr/w reset00000000 bit76543210 linearity_cal[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
519 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 29.8.20 debug control name: dbgctrl offset: 0x2a reset: 0x00 property: write-protected z bits 7:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? dbgrun: debug run 0: the adc is halted during debug mode. 1: the adc continues normal operation during debug mode. this bit can be changed only while the adc is disabled. this bit should be written only while a conversion is not ongoing. bit76543210 dbgrun accessrrrrrrrr/w reset00000000
520 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30. ac ? analog comparator 30.1 overview the atmel? sam d20 analog comparator (ac) supports tw o individual comparators. each comparator (comp) compares the voltage levels on two inputs, and provides a digital output based on this comparison. each comparator may be configured to generate interrupt requests and/or peripher al events upon several different combinations of input change. hysteresis and propagation delay are two important properties of the comparators; dynamic behavior. both parameters may be adjusted to achieve the optimal operation for each application. the input selection includes four shared analog port pins and several internal signals. each comparator output state can also be output on a pin for use by external devices. the comparators are always grouped in pairs on each port. the ac module may implement one pair. these are called comparator 0 (comp0) and comparator 1 (comp1). they hav e identical behaviors, but separate control registers. the pair can be set in window mode to compare a signal to a voltage range instead of a single voltage level. 30.2 features z two individual comparators z selectable propagation delay versus current consumption z selectable hysteresis z on/off z analog comparator outputs available on pins z asynchronous or synchronous z flexible input selection z four pins selectable for positive or negative inputs z ground (for zero crossing) z bandgap reference voltage z 64-level programmable vdd scaler per comparator z dac z interrupt generation on: z rising or falling edge z toggle z end of comparison z window function interrupt generation on: z signal above window z signal inside window z signal below window z signal outside window z event generation on: z comparator output z window function inside/outside window z optional digital filter on comparator output z low-power option z single-shot support
521 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.3 block diagram figure 30-1. analog comparator block diagram 30.4 signal description refer to ?i/o multiplexing and considerations? on page 15 for details on the pin mapping for this peripheral. one signal can be mapped on several pins. 30.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 30.5.1 i/o lines using the ac?s i/o lines requires the i/o pins to be configured. refer to the port chapter for details. refer to ?port? on page 289 for details. 30.5.2 power management the ac will continue to operate in any sleep mode where the selected source clock is running. the ac?s interrupts can be used to wake up the device from sleep modes. the events can trigger other operations in the system without exiting sleep modes. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. interrupt mode enable enable hysteresis hysteresis dac vdd scaler bandgap + - + - cmp0 cmp1 interrupts events gclk_ac ain3 ain2 ain1 ain0 comp0 comp1 compctrln winctrl interrupt sensitivity control & window function signal name type description ain[3..0] analog input comparator inputs cmp[1..0] digital output comparator outputs
522 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.5.3 clocks the ac bus clock (clk_ac_apb) can be enabled and disabl ed in the power manager, and the default state of the clk_ac_apb can be found in the peripheral clock masking section of ?pm ? power manager? on page 105 . two generic clocks (gclk_ac_dig and gclk_ac_ana) are us ed by the ac. the digital clock (gclk_ac_dig) is required to provide the sampling rate for the comparators, while the analog clock (gclk_ac_ana) is required for low- voltage operation (vdd < 2.5v) to ensure that the resistance of the analog input multiplexors remains low. these clocks must be configured and enabled in the generic clock controller before using the peripheral. refer to ?gclk ? generic clock controller? on page 83 for details. these generic clocks are asynchronous to the clk_ac_apb clock. due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. refer to ?synchronization? on page 530 for further details. 30.5.4 interrupts the interrupt request line is connected to the interrupt controller. using the ac interrupts requires the interrupt controller to be configured first. refer to ?nested vector interrupt controller? on page 28 for details. 30.5.5 events the events are connected to the event system. using the events requires the event system to be configured first. refer to ?evsys ? event system? on page 314 for details. 30.5.6 debug operation when the cpu is halted in debug mode, the peripheral continue s normal operation. if the peripheral is configured in a way that requires it to be periodically serviced by the cpu through interrupts or similar, improper operation or data loss may result during debugging. 30.5.7 register access protection all registers with write-access are optionally write-protected by the peripheral access controller (pac), except the following registers: z control b register (ctrlb) z interrupt flag register (intflag) write-protection is denoted by the write-protected property in the register description. write-protection does not apply for accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details. 30.5.8 analog connections each comparator has up to four i/o pins that can be used as analog inputs. each pair of comparators shares the same four pins. these pins must be configured for analog operation before using them as comparator inputs. any internal reference source, such as a bandgap reference voltage or the dac, must be configured and enabled prior to its use as a comparator input. 30.5.9 other dependencies not applicable. 30.6 functional description 30.6.1 principle of operation each comparator has one positive input and one negative input. each positive input may be chosen from a selection of analog input pins. each negative input may be chosen from a select ion of analog input pins or internal inputs, such as a
523 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 bandgap reference voltage. the digital output from the comparator is one when the difference between the positive and the negative input voltage is positive, and zero otherwise. the individual comparators can be used independently (nor mal mode) or grouped in pairs to generate a window comparison (window mode). 30.6.2 basic operation 30.6.2.1 initialization before enabling the ac, the input and output events must be configured in the event control register (evctrl). these settings cannot be changed while the ac is enabled. each individual comparator must also be configured by its respective comparator contro l register (compctrlx) before that comparator is enabled. these settings cannot be changed while the comparator is enabled. z select the desired measurement mode with compctrlx.single. see ?basic operation? on page 523 for more details z select the desired hysteresis with compctrlx.hyst. see ?input hysteresis? on page 527 for more details z select the comparator speed versus power with compctrlx.speed. see ?propagation delay vs. power consumption? on page 527 for more details z select the interrupt source with compctrlx.intsel z select the positive and negative input sources with t he compctrlx.muxpos and compctrlx.muxneg bits. see section ?selecting comparator inputs? on page 525 for more details z select the filtering option with compctrlx.flen 30.6.2.2 enabling, disabling and resetting the ac is enabled by writing a one to the enable bit in the control a register (ctrla.enable). the individual comparators must be also enabled by writing a one to the enable bit in the comparator x control registers (compctrlx.enable). the ac is disabled by writing a zero to ctrla.enable. this will also disable the individual comparators, but will not clear their compctrlx.enable bits. the ac is reset by writing a one to the software reset bit in the control a register (ctrla.swrst). all registers in the ac, except debug, will be reset to their initial state, and the ac will be disabled. refer to the register for details. 30.6.2.3 basic operation each comparator channel can be in one of two different measurement modes, determined by the single bit in the comparator x control register (compctrlx.single): z continuous measurement z single-shot after being enabled, a start-up delay is required before the resu lt of the comparison is ready. this start-up time is measured automatically to account for environmental changes, such as temperature or voltage supply level, and is specified in . during the start-up time, the comp output is not available. if the supply voltage is below 2.5v, the start-up time is also dependent on the voltage doubler. if the supply voltage is guaranteed to be above 2.5v, the voltage doubler can be disabled by writing the low-power mux bit in the control a register (ctrla.lpmux) to one. the comparator can be configured to generate interrupts when the output toggles, when the output changes from zero to one (rising edge), when the output changes from one to zero (falling edge) or at the end of the comparison. an end-of- comparison interrupt can be used with the single-shot mode to chain further events in the system, regardless of the state of the comparator outputs. the interrupt mode is set by t he interrupt selection bit group in the comparator control register (compctrlx.intsel). events are generated using the comparator output state, regardless of whether the interrupt is enabled or not.
524 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 continuous measurement continuous measurement is selected by writing compctrlx.si ngle to zero. in continuous mode, the comparator is continuously enabled and performing comparisons. this ensures that the result of the latest comparison is always available in the current state bit in the status a regist er (statusa.statex). after t he start-up time has passed, a comparison is done and statusa is updated. the com parator x ready bit in the status b register (statusb.readyx) is set, and the appr opriate peripheral events and interrupts are also generated. new comparisons are performed continuously until the compctrlx.enable bit is written to zero. the start-up time applies only to the first comparison. in continuous operation, edge detection of the comparator output for interrupts is done by comparing the current and previous sample. the sampling rate is the gclk_ac_dig frequency. an example of continuous measurement is shown in figure 30-2 . figure 30-2. continuous measurement example for low-power operation, comparisons can be performed duri ng sleep modes without a clock. the comparator is enabled continuously, and changes in the state of the comparator are detected asynchronously. when a toggle occurs, the power manager will start gclk_ac_dig to register the appropriate peripheral events and interrupts. the gclk_ac_dig clock is then disabled again automatically, unless configured to wake up the system from sleep. single-shot single-shot operation is selected by writing compctrlx.sing le to one. during single-shot operation, the comparator is normally idle. the user starts a single comparison by writi ng a one to the respective start comparison bit in the write- only control b register (ctrlb.startx) . the comparator is enabled, and after the start-up time has passed, a single comparison is done and statusa is updated. appropriate per ipheral events and interrupts are also generated. no new comparisons will be performed. writing a one to ctrlb.startx also clears the comparator x ready bit in the status b register (statusb.readyx). statusb.readyx is set automatically by hardware when the single comparison has completed. to remove the need for polling, an additional means of starting the comparison is also available. a read of the status c register (statusc) will start a comparison on all comparators currently configur ed for single-shot operation. the read will stall the bus until all enabled comparators are ready. if a com parator is already busy with a comparison, the read will stall until the current comparison is compete, and a new comparison will not be started. a single-shot measurement can also be triggered by the event system. writing a one to the comparator x event input bit in the event control register (evctrl.compeix) enables triggering on incoming peripheral events. each comparator can be triggered independently by separate events. event-trigger ed operation is similar to user-triggered operation; the difference is that a peripheral event from another hardwar e module causes the hardware to automatically start the comparison and clear statusb.readyx. to detect an edge of the comparator output in single-shot operation for the purpose of interrupts, the result of the current measurement is compared with the result of the previous measurement (one sampling peri od earlier). an example of single-shot operation is shown in figure 30-3 . gclk_ac statusb.readyx sampled comparator output compctrlx.enable t startup write ?1? 2-3 cycles
525 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 30-3. single-shot example for low-power operation, event-triggered measurements can be performed during sleep modes. when the event occurs, the power manager will start gclk_ac_dig. the comparator is enabled, and after the startup time has passed, a comparison is done and appropriate peripheral events and interrupts are also generated. the comparator and gclk_ac_dig are then disabled again automatically, unl ess configured to wake up the system from sleep. 30.6.3 selecting co mparator inputs each comparator has one positive and one negative input. the posit ive input is fed from an external input pin (ainx). the negative input can be fed either from an external input pin (a inx) or from one of the several internal reference voltage sources common to all comparators. the us er selects the input source as follows: z the positive input is selected by the positive input mux select bit group in the comparator control register (compctrlx.muxpos) z the negative input is selected by the negative input mux select bit group in the comparator control register (compctrlx.muxneg) in the case of using an external i/o pin, the selected pin must be configured for analog usage in the port controller by disabling the digital input and output. the switching of the anal og input multiplexors is controlled to minimize crosstalk between the channels. the input selection must be changed only while the individual comparator is disabled. 30.6.4 window operation each comparator pair can be configured to work together in window mode. in this mode, a voltage range is defined, and the comparators give information about whether an input si gnal is within this range or not. window mode is enabled by the window enable x bit in the window control register (w inctrl.wenx). both comparators in a pair must have the same measurement mode setting in their respective comparator control registers (compctrlx.single). to physically configure the pair of comparators for window mode, the same i/o pin should be chosen for each comparator?s positive input to create the shared input signal. the negative inputs define the range for the window. in figure 30-4 , comp0 defines the upper limit and comp1 defines the lower limit of the window, as shown but the window will also work in the opposite configuration with comp0 lower and comp1 higher. the current state of the window function is available in the window x state bit group of the status register (status.wstatex). window mode can be configured to generate interrupts when the input voltage changes to below the window, when the input voltage changes to above the window, when the input voltage changes into the window or when the input voltage changes outside the window. the interrupt selections are set by the window interrupt selection bit group in the window control register (winctrl.wintselx[ 1:0]). events are generated using the inside/outside state of the window, regardless of whether the interrupt is enabled or not. note t hat the individual comparator outputs, interrupts and events continue to function normally during window mode. when the comparators are configured for window mode and single-shot mode, measurements are performed simultaneously on both comparators. writing a one to either start comparison bit in the control b register (ctrlb.startx) starts a measur ement. likewise either peripheral event can start a measurement. gclk_ac statusb.readyx sampled comparator output ctrlb.startx t startup write ?1? t startup write ?1? 2-3 cycles 2-3 cycles
526 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 30-4. comparators in window mode 30.6.5 voltage doubler the ac contains a voltage doubler that can reduce the resistance of the analog multiplexors when the supply voltage is below 2.5v. the voltage doubler is normally switched on/off automatically based on the supply level. when enabling the comparators, additional start-up time is required for the vo ltage doubler to settle. if the supply voltage is guaranteed to be above 2.5v, the voltage doubler can be disabled by writi ng the low-power mux bit in the control a register (ctrla.lpmux) to one. disabling the voltage doubl er saves power and reduces the start-up time. 30.6.6 vdd scaler the vdd scaler generates a reference voltage that is a fraction of the device?s supply voltage, with 64 levels. one independent voltage channel is dedicated for each comparator. the scaler is enabled when a comparator?s negative input mux bitgroup in its comparator control register (c ompctrlx.muxneg) is set to five and the comparator is enabled. the voltage of each channel is selected by the value bit group in the scaler x registers (scalerx.value[5:0]). + - + - state0 state1 wstate[1:0] interrupts events input signal upper limit of window comp0 comp1 interrupt sensitivity control & window function lower limit of window
527 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 30-5. vdd scaler 30.6.7 input hysteresis application software can selectively enable/disable hysteresis for the comparison. applying hysteresis will help prevent constant toggling of the output,which can be caused by noise when the input signals are close to each other. hysteresis is enabled for each comparator individually by the hyster esis mode bit in the comparator x control register (compctrlx.hyst). hysteresis is available only in continuous mode (compctrlx.single=0). 30.6.8 propagation delay vs. power consumption it is possible to trade off comparison speed for power efficiency to get the shortest possible propagation delay or the lowest power consumption. the speed setting is configured for each comparator individually by the speed bit group in the comparator x control register (com pctrlx.speed). the speed bits select the amount of bias current provided to the comparator, and as such will also affect the start-up time. 30.6.9 filtering the output of the comparators can be digitally filtered to re duce noise using a simple digital filter. the filtering is determined by the filter length bits in the comparator control x register (compctrlx.flen), and is independent for each comparator. filtering is selectable from none, 3-bit majority (n=3) or 5-bit majority (n=5) functions. any change in the comparator output is considered valid only if n/2+1 out of the last n samples agree. the filter sampling rate is the clk_ac frequency scaled by the prescaler setting in the control a register (ctrla.prescaler). note that filtering creates an additional delay of n-1 sa mpling cycles from when a comparison is started until the comparator output is validated. for continuous mode, the first valid output will occur when the required number of filter samples is taken. subsequent outputs will be generated every cycle based on the current sample plus the previous n-1 samples, as shown in figure 30-6 . for single-shot mode, the comparison completes after the nth filter sample, as shown in figure 30-7 . compctrlx.muxneg == 5 scalerx. value to compx 6
528 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 figure 30-6. continuous mode filtering figure 30-7. single-shot filtering during sleep modes, filtering is supported only for single-s hot measurements. filtering must be disabled if continuous measurements will be done during sleep modes, or the resulting interrupt/event may be generated incorrectly. 30.6.10 comparator output the output of each comparator can be routed to an i/o pin by setting the output bit group in the comparator control x register (compctrlx.out). this allows the comparator to be used by external circuitry. either the raw, non- synchronized output of the comparator or the clk_ac-synchr onized version, including filtering, can be used as the i/o signal source. the output appears on the corresponding cmp[x] pin. 30.6.11 offset compensation the swap bit in the comparator control registers (compctr lx.swap) controls switching of the input signals to a comparator's positive and negative terminals. when the compar ator terminals are swapped, the output signal from the comparator is also inverted, as shown in figure 30-8 . this allows the user to measure or compensate for the comparator input offset voltage. as part of the input selection, compctrlx.swap can be changed only while the comparator is disabled. figure 30-8. input swapping for offset compensation sampling clock sampled comparator output 3-bit majority filter output 5-bit majority filter output sampling clock 3- bit sampled comparator output 3-bit majority filter output start 5- bit sampled comparator output 5-bit majority filter output t sut m u xp os m u xne g + - compx s wap enable hy s tere s i s s wa p c mpx compctrlx
529 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.6.12 interrupts the peripheral has the following interrupt sources: z comparator: comp0, comp1( intenclr, intset, intflag) z window: win0(intenclr, intset, intflag) comparator interrupts are generated based on the conditions selected by the interrupt selection bit group in the comparator control registers (com pctrlx.intsel). window interrupt s are generated based on the conditions selected by the window interrupt selection bit group in the window control register (winctrl.wintsel[1:0]). each interrupt source has an interrupt flag associated with i t. the interrupt flag in the interrupt flag status and clear register (intflag) is set when the interrupt condition occu rs. each interrupt can be individually enabled by writing a one to the corresponding bit in the interrupt enable set regi ster (intenset), and disabled by writing a one to the corresponding bit in the interrupt enable clear register (int enclr). an interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset. an interrupt flag is cleared by writing a one to the corresponding bit in the intflag register. each peripheral can have one interrupt request line per interr upt source or one common interrupt request line for all the interrupt sources. if the peripheral has one common interrupt r equest line for all the interrupt sources, the user must read the intflag register to determine which interrupt condition is present. for details on clearing interrupt flags, refer to the intflag register description. note that interrupts must be globally enabled for interrupt requests to be generated. refer to ?nested vector interrupt controller? on page 28 for details. 30.6.13 events the peripheral can generate the following output events: z comparator: compeo0, compeo1(evctrl) z window: wineo0(evctrl) output events must be enabled to be generated. writing a one to an event output bit in the event control register (evctrl.compeox) enables the corresponding output event. wr iting a zero to this bit disables the corresponding output event. the events must be correctly routed in the event system. refer to ?evsys ? event system? on page 314 for details. the peripheral can take the following actions on an input event: z single-shot measurement z single-shot measurement in window mode input events must be enabled for the corresponding action to be taken on any input event. writing a one to an event input bit in the event control register (evctrl.compeix) enables the corresponding action on input event. writing a zero to a bit disables the corresponding action on input event. note that if several events are connected to the peripheral, the enabled action will be taken on any of the incoming events. the events must be correctly routed in the event system. refer to ?evsys ? event system? on page 314 for details. when evctrl.compeix is one, the event will start a com parison on compx after the start-up time delay. in normal mode, each comparator responds to its corresponding i nput event independently. for a pair of comparators in window mode, either comparator event will trigger a comparison on both comparators simultaneously. 30.6.14 sleep mode operation the run in standby bit in the control a register (ctrla.runstdby) controls the behavior of the ac during standby sleep mode. when the bit is zero, the comparator pair is disabled during sleep, but maintains its current configuration. when the bit is one, the comparator pair continues to operat e during sleep. note that when runstdby is zero, the analog blocks are powered off for the lowest power consumption. this necessitates a start-up time delay when the system returns from sleep.
530 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 when runstdby is one, any enabled ac interrupt source c an wake up the cpu. however, single-shot comparisons will be triggerable by events only while the cpu is idle. the ac can also be used during sleep modes where the clock used by the ac is disabled, provided that the ac is still powered (not in shutdown). in this case, the behavior is slightly different and depends on the measurement mode, as listed in table 30-1 . table 30-1. sleep mode operation 30.6.14.1 continuous measurement during sleep when a comparator is enabled in continuous measurement mode and gclk_ac_dig is disabled during sleep, the comparator will remain continuously enabled and will function asynchronously. the current state of the comparator is asynchronously monitored for changes. if an edge matching the interrupt condition is found, gclk_ac_dig is started to register the interrupt condition and generate events. if th e interrupt is enabled in the interrupt enable registers (intenclr/set), the ac can wake up the device; other wise gclk_ac_dig is disabled until the next edge detection. filtering is not possible with this configuration. figure 30-9. continuous mode sleepwalking 30.6.14.2 single-shot measurement during sleep for low-power operation, event-triggered measurements can be performed during sleep modes. when the event occurs, the power manager will start gclk_ac_dig. the comparator is enabled, and after the start-up time has passed, a comparison is done, with filtering if desired, and the appr opriate peripheral events and interrupts are also generated, as shown in figure 30-10 the comparator and gclk_ac_dig are then dis abled again automatically, unless configured to wake the system from sleep. filtering is allowed with this configuration. figure 30-10.single -shot sleepwalking 30.6.15 synchronization due to the asynchronicity between clk_module_apb and gclk_module, some registers must be synchronized when accessed. a register can require: z synchronization when written z synchronization when read compctrlx.mode runstdby=0 runstdby=1 0 (continuous) compx disabled gclk_ac_dig stopped, compx enabled 1 (single-shot) compx disabled gclk_ac_dig stopped, compx enabled only when triggered by an input event gclk_ac comparator output or event comparator state gclk_ac comparator output or event input event t startup t startup
531 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z synchronization when written and read z no synchronization when executing an operation that requires synchronization, the synchronization busy bit in the status register (status.syncbusy) will be set immediately, and cleared when synchronization is complete.
532 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.7 register summary offset name bit pos. 0x00 ctrla 7:0 runstdby enable swrst 0x01 ctrlb 7:0 start1 start0 0x02 evctrl 7:0 wineo0 compeo1 compeo0 0x03 15:8 compei1 compei0 0x04 intenclr 7:0 win0 comp1 comp0 0x05 intenset 7:0 win0 comp1 comp0 0x06 intflag 7:0 win0 comp1 comp0 0x07 reserved 0x08 statusa 7:0 wstate0[1:0] state1 state0 0x09 statusb 7:0 syncbusy ready1 ready0 0x0a statusc 7:0 wstate0[1:0] state1 state0 0x0b reserved 0x0c winctrl 7:0 wintsel0[1:0] wen0 0x0d reserved 0x0e reserved 0x0f reserved 0x10 compctrl0 7:0 intsel[1:0] speed[1:0] single enable 0x11 15:8 swap muxpos[1:0] muxneg[2:0] 0x12 23:16 hyst out[1:0] 0x13 31:24 flen[2:0] 0x14 compctrl1 7:0 intsel[1:0] speed[1:0] single enable 0x15 15:8 swap muxpos[1:0] muxneg[2:0] 0x16 23:16 hyst out[1:0] 0x17 31:24 flen[2:0] 0x18 reserved ... reserved 0x1f reserved 0x20 scaler0 7:0 value[5:0] 0x21 scaler1 7:0 value[5:0]
533 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each individual register description. refer to ?register access protection? on page 522 for details. some registers require synchronization when read and/or wr itten. synchronization is denoted by the write-synchronized or the read-synchronized property in each individual register description. refer to ?synchronization? on page 530 for details. some registers are enable-protected, meaning they can be wr itten only when the ac is disabled. enable-protection is denoted by the enable-protected property in each individual register description. 30.8.1 control a name: ctrla offset: 0x00 reset: 0x00 property: write-protected z -bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? runstdby: run in standby this bit controls the behavior of the comparators during standby sleep mode. 0: the comparator pair is disabled during sleep. 1: the comparator pair continues to operate during sleep. z bit 1 ? enable: enable 0: the ac is disabled. 1: the ac is enabled. each comparator must also be enabled individually by the enable bit in the comparator control register (compctrlx.enable). due to synchronization, there is delay from updating the register until the peripheral is enabled/disabled. the value written to ctrl.enable will read back immediately after being written. status.syncbusy is set. sta- tus.syncbusy is cleared when t he peripheral is enabled/disabled. z bit 0 ? swrst: software reset 0: there is no reset operation ongoing. 1: the reset operation is ongoing. writing a zero to this bit has no effect. writing a one to this bit resets all registers in the ac to their initial state, and the ac will be disabled. writing a one to ctrl.swrst will always take precedence, meaning that all other writes in the same write-oper- ation will be discarded. bit 76543210 runstdby enable swrst accessrrrrrr/wr/wr/w reset00000000
534 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 due to synchronization, there is a delay from writing ctrla.swrst until the reset is complete. ctrla.swrst and status.syncbusy will both be cl eared when the reset is complete.
535 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.8.2 control b name: ctrlb offset: 0x01 reset: 0x00 property: ? z bits 7:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 1:0 ? startx: comparator x start comparison writing a zero to this field has no effect. writing a one to startx starts a single-shot comparison on compx if both the single-shot and enable bits in the comparator x control register are one (compctrlx.s ingle and compctrlx.enable). if comparator x is not implemented, or if it is not enabled in single-shot mode, writing a one has no effect. this bit always reads as zero. bit 76543210 start1 start0 accessrrrrrrww reset00000000
536 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.8.3 event control name: evctrl offset: 0x02 reset: 0x0000 property: write-protected, enable-protected z bits 15:10 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 9:8 ? compeix: co mparator x event input note that several actions can be enabled for incoming events. if several events are connected to the peripheral, the enabled action will be taken for any of the incoming events. there is no way to tell which of the incoming events caused the action. these bits indicate whether a comparison will start or not on any incoming event. 0: comparison will not start on any incoming event. 1: comparison will start on any incoming event. z bits 7:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 4 ? wineo0: window 0 event output enable this bit indicates whether the window 0 f unction can generate a peripheral event or not. 0: window 0 event is disabled. 1: window 0 event is enabled. z bits 3:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 1:0 ? compeox: compar ator x event output enable these bits indicate whether the comparator x output can generate a peripheral event or not. 0: compx event generation is disabled. 1: compx event generation is enabled. bit 151413121110 9 8 compei1 compei0 accessrrrrrrr/wr/w reset00000000 bit 76543210 wineo0 compeo1 compeo0 access r r r r/w r r r/w r/w reset00000000
537 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.8.4 interrupt enable clear this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable set register (intenset). name: intenclr offset: 0x04 reset: 0x00 property: write-protected z bits 7:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 4 ? win0: window 0 interrupt enable reading this bit returns the state of the window 0 interrupt enable. 0: the window 0 interrupt is disabled. 1: the window 0 interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit disables the window 0 interrupt. z bits 3:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 1:0 ? compx: comparator x interrupt enable reading this bit returns the state of the comparator x interrupt enable. 0: the comparator x interrupt is disabled. 1: the comparator x interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit disables the comparator x interrupt. bit76543210 win0 comp1 comp0 access r r r r/w r r r/w r/w reset00000000
538 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.8.5 interrupt enable set this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear register (intenclr). name: intenset offset: 0x05 reset: 0x00 property: write-protected z bits 7:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z w bit 4 ? win0: window 0 interrupt enable reading this bit returns the state of the window 0 interrupt enable. 0: the window 0 interrupt is disabled. 1: the window 0 interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit enables the window 0 interrupt. z bits 3:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 1:0 ? compx: comparator x interrupt enable reading this bit returns the state of the comparator x interrupt enable. 0: the comparator x interrupt is disabled. 1: the comparator x interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the ready interrupt bit and enable the ready interrupt. bit 76543210 win0 comp1 comp0 access r r r r/w r r r/w r/w reset00000000
539 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.8.6 interrupt flag status and clear name: intflag offset: 0x06 reset: 0x00 property: ? z bits 7:5 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 4 ? win0: window 0 this flag is set according to the window 0 interrupt selection bit group in the winctrl register (winc- trl.wintsel0) and will generate an interrupt if intenclr/set.win0 is also one. writing a zero to this bit has no effect. writing a one to this bit clears the window 0 interrupt flag. z bits 3:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 1:0 ? compx: comparator x reading this bit returns the status of the comparator x interrupt flag. if comparator x is not implemented, compx always reads as zero. this flag is set according to the interrupt selection bit group in the comparator x control register (compc- trlx.intsel) and will generate an interrupt if intenclr/set.compx is also one. writing a zero to this bit has no effect. writing a one to this bit clears the comparator x interrupt flag. bit 76543210 win0 comp1 comp0 access r r r r/w r r r/w r/w reset00000000
540 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.8.7 status a name: statusa offset: 0x08 reset: 0x00 property: ? z bits 7:6 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 5:4 ? wstate0[1:0]: window 0 current state these bits show the current state of the signal if the window 0 mode is enabled, according to table 30-2 . if the win- dow 0 function is not implemented, wstate0 always reads as zero. table 30-2. window mode current state z bits 3:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 1:0 ? statex: comp arator x current state this bit shows the current state of the output signal fr om compx. statex is vali d only when statusb.readyx is one. bit76543210 wstate0[1:0] state1 state0 accessrrrrrrrr reset00000000 value name description 0x0 above signal is above window 0x1 inside signal is inside window 0x2 below signal is below window 0x3 ? reserved
541 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.8.8 status b name: statusb offset: 0x09 reset: 0x00 property: ? z bit 7 ? syncbusy: synchronization busy this bit is cleared when the synchronization of registers between the clock domains is complete. this bit is set when the synchronization of registers between clock domains is started. z bits 6:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 1:0 ? readyx: comparator x ready this bit is cleared when the comparator x output is not ready. this bit is set when the comparator x output is ready. bit 76543210 syncbusy ready1 ready0 accessrrrrrrrr reset00000000
542 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.8.9 status c statusc is a copy of statusa (see statusa register), with the additional feature of automatically starting single- shot comparisons. a read of statusc will start a compar ison on all comparators currently configured for single-shot operation. the read will stall the bus until all enabled compar ators are ready. if a comparator is already busy with a comparison, the read will stall until the current comparis on is compete, and a new comparison will not be started. name: statusc offset: 0x0a reset: 0x00 property: ? z bits 7:6 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 5:4 ? wstate0[1:0]: window 0 current state these bits show the current state of the signal if the window 0 mode is enabled. if the window 0 function is not implemented, wstate0 always reads as zero. table 30-3. window mode current state z bits 3:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 1:0 ? statex: comp arator x current state this bit shows the current state of the output signal from compx. if comparator x is not implemented, statex always reads as zero. statex is only valid when statusb.readyx is one. bit76543210 wstate0[1:0] state1 state0 accessrrrrrrrr reset00000000 value name description 0x0 above signal is above window 0x1 inside signal is inside window 0x2 below signal is below window 0x3 ? reserved
543 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.8.10 window control name: winctrl offset: 0x0c reset: 0x00 property: synchronized, write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 2:1 ? wintsel0: window 0 interrupt selection these bits configure the interrupt mode for the comparator window 0 mode. table 30-4. window 0 interrupt selection z bit 0 ? wen0: window 0 mode enable 0: window mode is disabled for comparators 0 and 1. 1: window mode is enabled for comparators 0 and 1. bit 76543210 wintsel0[1:0] wen0 accessrrrrrr/wr/wr/w reset00000000 value name description 0x0 above interrupt on signal above window 0x1 inside interrupt on signal inside window 0x2 below interrupt on signal below window 0x3 outside interrupt on signal outside window
544 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.8.11 scaler x name: scalerx offset: 0x20+x*0x1 [x=0..1] reset: 0x00 property: write-protected z bits 7:6 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 5:0 ? value[5:0]: scaler value these bits define the scaling factor for channel x of the v dd voltage scaler. the output voltage, v scale , is: bit 76543210 value[5:0] access r r r/w r/w r/w r/w r/w r/w reset00000000 v scale v dd value 1 + () ? 64 ------------------------------------------------- - =
545 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 30.8.12 comparator control x the configuration of comparator x is protected while comparator x is enabled (compctrlx.enable = 1). changes to the other bits in compctrlx can only occur when compctrlx.enable is zero. name: compctrlx offset: 0x10+x*0x4 [x=0..1] reset: 0x00000000 property: write-protected z bits 31:27 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 26:24 ? flen[2:0]: filter length these bits configure the filtering for comparator x. compctrlx.flen can only be written while compc- trlx.enable is zero. table 30-5. filter length bit 3130292827262524 flen[2:0] accessrrrrrr/wr/wr/w reset00000000 bit 2322212019181716 hyst out[1:0] access r r r r r/w r r/w r/w reset00000000 bit 151413121110 9 8 swap muxpos[1:0] muxneg[2:0] access r/w r r/w r/w r r/w r/w r/w reset00000000 bit 76543210 intsel[1:0] speed[1:0] single enable access r r/w r/w r r/w r/w r/w r/w reset00000000 value name description 0x0 off no filtering
546 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 z bits 23:20 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 19 ? hyst: hysteresis enable this bit indicates the hysteresis mode of comparator x. hysteresis is available only for continuous mode (compc- trlx.single=0). compctrlx.hyst can be wri tten only while compctrlx.enable is zero. 0: hysteresis is disabled. 1: hysteresis is enabled. z bit 18 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 17:16 ? out[1:0]: output these bits configure the output selection for comparat or x. compctrlx.out can be written only while compc- trlx.enable is zero. table 30-6. output selection z bit 15 ? swap: swap inputs and invert this bit swaps the positive and negative inputs to cmpx and inverts the output. this function can be used for offset cancellation. compctrlx.swap can be writt en only while compctrlx.enable is zero. 0: the output of muxpos connects to the positive input, and the output of muxneg connects to the negative input. 1: the output of muxneg connects to the positive input, and the output of muxpos connects to the negative input. z bit 14 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 13:12 ? muxpos[1:0]: positive input mux selection these bits select which input will be connected to the po sitive input of comparator x. compctrlx.muxpos can be written only while compctrlx.enable is zero. 0x1 maj3 3-bit majority function (2 of 3) 0x2 maj5 5-bit majority function (3 of 5) 0x3-0x7 n/a reserved value name description 0x0 off the output of cmpn is not routed to the cmpn i/o port 0x1 async the asynchronous output of cmpn is routed to the cmpn i/o port 0x2 sync the synchronous output (including filtering) of cmpn is routed to the cmpn i/o port 0x3 n/a reserved value name description
547 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table 30-7. positive input mux selection z bit 11 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 10:8 ? muxneg[2:0]: negative input mux selection these bits select which input will be connected to the negative input of comparator x. compctrlx.muxneg can only be written while compctrlx.enable is zero. table 30-8. negative input mux selection z bit 7 ? reserved this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 6:5 ? intsel[1:0]: interrupt selection these bits select the condition for comparator x to generate an interrupt or event. compctrlx.intsel can be written only while compctrlx.enable is zero. table 30-9. interrupt selection z bit 4 ? reserved value name description 0x0 pin0 i/o pin 0 0x1 pin1 i/o pin 1 0x2 pin2 i/o pin 2 0x3 pin3 i/o pin 3 value name description 0x0 pin0 i/o pin 0 0x1 pin1 i/o pin 1 0x2 pin2 i/o pin 2 0x3 pin3 i/o pin 3 0x4 gnd ground 0x5 vscale vdd scaler 0x6 bandgap internal bandgap voltage 0x7 dac dac output value name description 0x0 toggle interrupt on comparator output toggle 0x1 rising interrupt on comparator output rising 0x2 falling interrupt on comparator output falling 0x3 eoc interrupt on end of comparison (single-shot mode only)
548 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 this bit is unused and reserved for future use. for compatibility with future devices, always write this bit to zero when this register is written. this bit will always return zero when read. z bits 3:2 ? speed[1:0]: speed selection this bit indicates the speed/propagation delay mode of co mparator x. compctrlx.sp eed can be written only while compctrlx.enable is zero. table 30-10. speed selection z bit 1 ? single: single-shot mode this bit determines the operation of comparator x. compctrlx.single can be written only while compc- trlx.enable is zero. 0: comparator x operates in continuous measurement mode. 1: comparator x operates in single-shot mode. z bit 0 ? enable: enable writing a zero to this bit disables comparator x. writing a one to this bit enables comparator x. after writing to this bit, the value read back will not change until the action initiated by the writing is complete. due to synchronization, there is a latency of at least two gclk_ac_dig clock cycles from updating the register until the comparator is enabled/disabled. the bit will continue to read the previous state while the change is in progress. writing a one to compctrlx.enable will prevent further changes to the other bits in compctrlx. these bits remain protected until compctrlx.enable is written to zero and the write is synchronized. value name description 0x0 low low speed 0x1 high high speed 0x2-0x3 reserved
549 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31. dac ? digital-to-analog converter 31.1 overview the digital-to-analog converter (dac) converts a digita l value to a voltage. the dac has one channel with 10-bit resolution, and it is capable of converting up to 350,000 samples per second (ksps). 31.2 features z dac with 10-bit resolution z up to 350ksps conversion rate z multiple trigger sources z high-drive capabilities z output can be used as input to the analog comparator (ac) 31.3 block diagram figure 31-1. dac block diagram 31.4 signal description refer to ?i/o multiplexing and considerations? on page 15 for the pin mapping of this peripheral. one signal can be mapped on several pins. dac10 output driver ac av cc start v out event control evctrl data ctrla empty int1v vrefp databuf ctrlb status adc signal name type description vout analog output dac output vrefp analog input external reference
550 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.5 product dependencies in order to use this peripheral, other parts of the system must be configured correctly, as described below. 31.5.1 i/o lines using the dac?s i/o lines requires the i/o pins to be configured using the port configuration (port). refer to ?port? on page 289 for details. 31.5.2 power management the dac will continue to operate in any sleep mode where the selected source clock is running. the dac interrupts can be used to wake up the device from sleep modes. the events can trigger other operations in the system without exiting sleep modes. refer to ?pm ? power manager? on page 105 for details on the different sleep modes. 31.5.3 clocks the dac bus clock (clk_dac_apb) can be enabled and dis abled in the power manager, and the default state of clk_dac_apb can be found in the peripheral clock masking section in ?pm ? power manager? on page 105 . a generic clock (gclk_dac) is required to clock the dac. this clock must be configured and enabled in the generic clock controller before using the dac. refer to ?gclk ? generic clock controller? on page 83 for details. this generic clock is asynchronous to the bus clock (clk_dac). due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. refer to ?synchronization? on page 553 for further details. 31.5.4 dma not applicable. 31.5.5 interrupts the interrupt request line is connected to the interrupt c ontroller. using the dac interrupts requires the interrupt controller to be configured first. refer to ?nested vector interrupt controller? on page 28 for details. 31.5.6 events the events are connected to the event system. refer to ?evsys ? event system? on page 314 for details on how to configure the event system. 31.5.7 debug operation when the cpu is halted in debug mode the dac continues normal operation. if the dac is configured in a way that requires it to be periodically serviced by the cpu through inte rrupts or similar, improper operation or data loss may result during debugging. 31.5.8 register access protection all registers with write-access are optionally write-protected by the peripheral access controller (pac), except the following register: z interrupt flag status and clear register (intflag) write-protection is denoted by the write-protection property in the register description. when the cpu is halted in debug mode, all writ e-protection is automatically disabled. write-protection does not apply for accesses through an external debugger. refer to ?pac ? peripheral access controller? on page 31 for details.
551 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.5.9 analog connections not applicable. 31.6 functional description 31.6.1 principle of operation the digital-to-analog converter (dac) converts the digital value written to the data register (data) into an analog voltage on the dac output. by default, a conversion is star ted when new data is written to data, and the corresponding voltage is available on the dac output after the conversion time. it is also possible to enable events from the event system to trigger the conversion. 31.6.2 basic operation 31.6.2.1 initialization before enabling the dac, it must be configured by selecting the voltage reference using the reference selection bits in the control b register (ctrlb.refsel). 31.6.2.2 enabling, disabling and resetting the dac is enabled by writing a one to the enable bit in t he control a register (ctrla.e nable). the dac is disabled by writing a zero to ctrla.enable. the dac is reset by writing a one to the software reset bit in the control a register (ctrla.s wrst). all registers in the dac will be reset to their initial state, and the dac will be disabled. refer to the ctrla register for details. 31.6.2.3 enabling the output buffer to enable the dac output on the v out pin, the output driver must be enabled by writing a one to the external output enable bit in the control b register (ctrlb.eoen). the dac output buffer provides a high-drive-strength output , and is capable of driving both resistive and capacitive loads. to minimize power consumption, the output buffer should be enabled only when external output is needed. 31.6.3 additional features 31.6.3.1 conversion range the conversion range is between gnd and the selected dac voltage reference. the default voltage reference is the internal 1v (int1v) reference voltage. the other volt age reference options are the 3.3v analog supply voltage (av cc = vddana) and the external voltage referenc e (vrefp). the voltage reference is selected by writing to the reference selection bits in the control b register (ctrlb.refsel) . the output voltage from the dac can be calculated using the following formula: 31.6.3.2 dac as an internal reference the dac output can be internally enabled as input to the analog comparator. this is enabled by writing a one to the internal output enable bit in the control b register (ctrlb .ioen). it is possible to have the internal and external output enabled simultaneously. the dac output can also be enabled as input to the analog-to-digital converter. in this case, the output buffer must be enabled. v dac data 0 x 3 ff ---------------- - vref ? =
552 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.6.3.3 data buffer the data buffer register (databuf) and the data register (data) are linked together to form a two-stage fifo. the dac uses the start conversion event to load data from databuf into data and start a new conversion. the start conversion event is enabled by writing a one to the star t event input bit in the event control register (evctrl.startei). if a start conversion event occurs when databuf is empty, an u nderrun interrupt request is generated if the underrun interrupt is enabled. if data are written to databuf when ev ctrl.startei is zero, the previous databuf value is automatically transferred to data, and a new conversion is started. the dac can generate a data buffer empty event when databuf becomes empty and new data can be loaded to the buffer. the data buffer empty event is enabled by writing a one to the empty event output bit in the event control register (evctrl.em ptyeo). a data buffer empty interrupt request is generated if the data buffer empty interrupt is enabled. 31.6.3.4 voltage pump when the dac is used at operating voltages lower than 2.5v, the voltage pump must be enabled. this enabling is done automatically, depending on operating voltage. the voltage pump can be disabled by writing a one to the voltage pump disable bit in the control b register (ctrlb.vpd). this can be used to reduce power consumption when the operating voltage is above 2.5v. the voltage pump uses the asynchronous gclk_dac clock, and requires that the clock frequency be at least four times higher than the sampling period. 31.6.3.5 sampling period as there is no automatic indication that a conversion is done, the sampling period must be greater than or equal to the specified conversion time. 31.6.4 dma operation not applicable. 31.6.5 interrupts the dac has the following interrupt sources: z data buffer empty z underrun z synchronization ready each interrupt source has an interrupt flag associated with i t. the interrupt flag in the interrupt flag status and clear register (intflag) is set when the interrupt condition occu rs. each interrupt can be individually enabled by writing a one to the corresponding bit in the interrupt enable set regi ster (intenset), and disabled by writing a one to the corresponding bit in the interrupt enable clear register (int enclr). an interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. the interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the dac is reset. see the register description for details on how to clear interrupt flags. the dac has one common interrupt request line for all the interrupt sources. the user must read the intflag register to determine which interrupt condition is present. note that interrupts must be globally enabled for interrupt requests to be generated. refer to ?nested vector interrupt controller? on page 28 for details. 31.6.6 events the dac can generate the following output events: z data buffer empty (empty)
553 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 writing a one to an event output bit in the event control register (evctrl.xxeo) enables the corresponding output event. writing a zero to this bit disables the corresponding output event. refer to ?evsys ? event system? on page 314 for details on configuring the event system. the dac can take the following actions on an input event: z start conversion (start) writing a one to an event input bit in the event control register (evctrl.xxei) enables the corresponding action on an input event. writing a zero to this bit disables the corresponding action on input event. note that if several events are connected to the dac, the enabled action will be taken on any of the incoming events. refer to ?evsys ? event system? on page 314 for details on configuring the event system. 31.6.7 sleep mode operation the generic clock for the dac is running in idle sleep mode. if the run in standby bit in the control a register (ctrla.runstdby) is one, the dac output buffer will keep its value in standby sleep mode. if ctrla.runstdby is zero, the dac output buffer will be disabled in standby sleep mode. 31.6.8 synchronization due to the asynchronicity between clk_dac_apb and gclk_dac, some registers must be synchronized when accessed. a register can require: z synchronization when written z synchronization when read z synchronization when written and read z no synchronization when executing an operation that requires synchronization, the synchronization busy bit in the status register (status.syncbusy) will be set immediately, and cleared when synchronization is complete. the synchronization ready interrupt can be used to signal when synchronization is complete. if an operation that requires synchronization is executed wh ile status.syncbusy is one, the bus will be stalled. all operations will complete successfully, but the cpu will be stalled and interrupts will be pending as long as the bus is stalled. the following bits need synchronization when written: z software reset bit in the control a register (ctrla.swrst) z enable bit in the control a register (ctrla.enable) z all bits in the data register (data) z all bits in the data buffer register (databuf) synchronization is denoted by the write-synchronized property in the register description. the following bits need synchronization when read: z all bits in the data register (data)
554 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.7 register summary offset name bit pos. 0x00 ctrla 7:0 runstdby enable swrst 0x01 ctrlb 7:0 refsel[1:0] vpd leftadj ioen eoen 0x02 evctrl 7:0 emptyeo startei 0x03 test 7:0 testen 0x04 intenclr 7:0 syncrdy empty underrun 0x05 intenset 7:0 syncrdy empty underrun 0x06 intflag 7:0 syncrdy empty underrun 0x07 status 7:0 syncbusy 0x08 data (1) 7:0 data[7:0] 0x09 15:8 data[9:8] 0x0a reserved 0x0b reserved 0x0c databuf (2) 7:0 databuf[7:0] 0x0d 15:8 databuf[9:8] 0x0e reserved 0x0f reserved 1. this register will have a different appearance depending on the value of ctrlb.leftadj. here, the right-adjusted form of dat a is shown. 2. this register will have a different appearance depending on the value of ctrlb.leftadj. here, the right-adjusted form of dat abuf is shown.
555 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.8 register description registers can be 8, 16 or 32 bits wide. atomic 8-, 16- and 32- bit accesses are supported. in addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit hal ves of a 16-bit register can be accessed directly. some registers are optionally write-protected by the perip heral access controller (pac). write-protection is denoted by the write-protected property in each individual register description. refer to ?register access protection? on page 550 for details. some registers require synchronization when read and/or written. synchronization is denoted by the synchronized property in each individual register description. refer to ?synchronization? on page 553 for details.
556 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.8.1 control a name: ctrla offset: 0x0 reset: 0x00 property: write-protected, write-synchronized z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? runstdby: run in standby 0: the dac output buffer is disabled in standby sleep mode. 1: the dac output buffer can be enabled in standby sleep mode. this bit is not synchronized. z bit 1 ? enable: enable 0: the peripheral is disabled or being disabled. 1: the peripheral is enabled or being enabled. due to synchronization, there is delay from writing ctrla.enable until the peripheral is enabled/disabled. the value written to ctrl.enable will read back immediately and the synchronization busy bit in the status register (status.syncbusy) will be set. status.syncbus y is cleared when the operation is complete. z bit 0 ? swrst: software reset 0: there is no reset operation ongoing. 1: the reset operation is ongoing. writing a zero to this bit has no effect. writing a one to this bit resets the all registers in the dac to their initial state, and the dac will be disabled. writing a one to ctrla.swrst will alwa ys take precedence, meaning that all other writes in the same write oper- ation will be discarded. due to synchronization, there is a delay from writing ctrla.swrst until the reset is complete. ctrla.swrst and status.syncbusy will both be cl eared when the reset is complete. bit76543210 runstdby enable swrst accessrrrrrr/wr/wr/w reset00000000
557 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.8.2 control b name: ctrlb offset: 0x1 reset: 0x00 property: write-protected z bits 7:6 ? refsel[1:0]: reference selection these bits select the reference voltage for the dac according to table 31-1 . table 31-1. reference selection z bits 5:4 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 3 ? vpd: voltage pump disable this bit controls the behavior of the voltage pump. 0: voltage pump is turned on/off automatically. 1: voltage pump is disabled. z bit 2 ? leftadj: left adjusted data this bit controls how the 10-bit conversion data is adjusted in the data and data buffer registers. 0: data and databuf regi sters are right-adjusted. 1: data and databuf registers are left-adjusted. z bit 1 ? ioen: internal output enable 0: internal dac output not enabled. 1: internal dac output enabled to be used by the ac. z bit 0 ? eoen: external output enable 0: the dac output is turned off. 1: the high-drive output buffer drives the dac output to the v out pin. bit76543210 refsel[1:0] vpd leftadj ioen eoen accessr/wr/w r r r/wr/wr/wr/w reset00000000 refsel[1:0] reference selection description 0x0 int1v internal 1.0v reference 0x1 avcc av cc 0x2 vrefp external reference 0x3 reserved
558 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.8.3 event control name: evctrl offset: 0x2 reset: 0x00 property: write-protected z bits 7:2 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 1 ? emptyeo: data bu ffer empty event output this bit indicates whether or not the data buffer empty event is enabled and will be generated when the data buf- fer register is empty. 0: data buffer empty event is disabled and will not be generated. 1: data buffer empty event is enabled and will be generated. z bit 0 ? startei: start conversion event input this bit indicates whether or not the start conversi on event is enabled and data are loaded from the data buffer register to the data register upon event reception. 0: a new conversion will not be triggered on an incoming event. 1: a new conversion will be triggered on an incoming event. bit76543210 emptyeo startei accessrrrrrrr/wr/w reset00000000
559 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.8.4 test name: test offset: 0x3 reset: 0x00 property: write-protected z bits 7:1 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 0 ? testen: test enable if the testen bit in the test register is written to one, the dac output buffer is bypassed and an unbuffered dac output is connected to the vout pad. this bit can be written only in test mode. bit76543210 testen accessrrrrrrrr/w reset00000000
560 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.8.5 interrupt enable clear this register allows the user to disable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable set register (intenset). name: intenclr offset: 0x4 reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? syncrdy: synchronization ready interrupt enable 0: the synchronization ready interrupt is disabled. 1: the synchronization ready interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the synchronization read y interrupt enable bit, which disables the synchroniza- tion ready interrupt. z bit 1 ? empty: data buff er empty interrupt enable 0: the data buffer empty interrupt is disabled. 1: the data buffer empty interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the data buffer empty interrupt enable bit, which disables the data buffer empty interrupt. z bit 0 ? underrun: underrun interrupt enable 0: the underrun interrupt is disabled. 1: the underrun interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will clear the underrun interrupt enable bit, which disables the underrun interrupt. bit76543210 syncrdy empty underrun accessrrrrrr/wr/wr/w reset00000000
561 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.8.6 interrupt enable set this register allows the user to enable an interrupt without doing a read-modify-write operation. changes in this register will also be reflected in the interrupt enable clear register (intenclr). name: intenset offset: 0x5 reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? syncrdy: synchronization ready interrupt enable 0: the synchronization ready interrupt is disabled. 1: the synchronization ready interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the synchronization ready interrupt enable bit, which enables the synchronization ready interrupt. z bit 1 ? empty: data buff er empty interrupt enable 0: the data buffer empty interrupt is disabled. 1: the data buffer empty interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the data buffer empty interrupt enable bit, which enables the data buffer empty interrupt. z bit 0 ? underrun: underrun interrupt enable 0: the underrun interrupt is disabled. 1: the underrun interrupt is enabled. writing a zero to this bit has no effect. writing a one to this bit will set the underrun interrupt enable bit, which enables the underrun interrupt. bit76543210 syncrdy empty underrun accessrrrrrr/wr/wr/w reset00000000
562 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.8.7 interrupt flag status and clear name: intflag offset: 0x6 reset: 0x00 property: write-protected z bits 7:3 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bit 2 ? syncrdy: synchronization ready this flag is cleared by writing a one to the flag. this flag is set on a 1-to-0 transition of the synchroniza tion busy bit in the status register (status.syncbusy), except when the transition is caused by an enable or a software reset, and will generate an interrupt request if intenclr/set.ready is one. writing a zero to this bit has no effect. writing a one to this bit will clear the synchronization ready interrupt flag. z bit 1 ? empty: data buffer empty this flag is cleared by writing a one to the flag or by writing new data to databuf. this flag is set when data is transferred from databuf to data, and the dac is ready to receive new data in databuf, and will generate an interrupt request if in tenclr/set.empty is one. writing a zero to this bit has no effect. writing a one to this bit will clear the data buffer empty interrupt flag. z bit 0 ? underrun: underrun this flag is cleared by writing a one to the flag. this flag is set when a start conversion event occurs when databuf is empty, and will generate an interrupt request if intenclr/set.underrun is one. writing a zero to this bit has no effect. writing a one to this bit will clear the underrun interrupt flag. bit76543210 syncrdy empty underrun accessrrrrrr/wr/wr/w reset00000000
563 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.8.8 status name: status offset: 0x7 reset: 0x00 property: read-synchronized z bit 7 ? syncbusy: synchronization busy status this bit is cleared when the synchronization of registers between the clock domains is complete. this bit is set when the synchronization of registers between clock domains is started. z bits 6:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. bit76543210 syncbusy accessrrrrrrrr reset00000000
564 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.8.9 data this register contains the 10-bit value that is converted to a voltage by the dac. the adjustment of these 10 bits within the 16-bit register is controlled by ctrlb.leftadj. mode: right adjusted name: data offset: 0x8 reset: 0x0000 property: write-synchronized, read-synchronized, write-protected z bits 15:10 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 9:0 ? data[9:0]: data these bits are the right-adjusted 10-bit va lue to convert (ctrlb.leftadj is zero). bit151413121110 9 8 data[9:8] accessrrrrrrr/wr/w reset00000000 bit76543210 data[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
565 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 mode: left adjusted name: data offset: 0x8 reset: 0x0000 property: write-synchronized, read-synchronized, write-protected z bits 15:6 ? data[9:0]: data these bits are the left-adjusted 10-bit va lue to convert (ctrlb.leftadj is one). z bits 5:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. bit151413121110 9 8 data[9:2] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 data[1:0] accessr/wr/wrrrrrr reset00000000
566 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 31.8.10 data buffer this register contains the 10-bit value that is transferred to data and converted to a voltage by the dac. the adjustment of these 10 bits within the 16-bit register is controlled by ctrlb.leftadj. mode: right adjusted name: databuf offset: 0xc reset: 0x0000 property: write-synchronized, write-protected z bits 15:10 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. z bits 9:0 ? databuf[9:0]: data buffer these bits are the right-adjusted 10-bit data buffer value (ctrlb.leftadj is zero). bit151413121110 9 8 databuf[9:8] accessrrrrrrr/wr/w reset00000000 bit76543210 databuf[7:0] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000
567 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 mode: left adjusted name: databuf offset: 0xc reset: 0x0000 property: write-synchronized, write-protected z bits 15:6 ? databuf[9:0]: data buffer these bits are the left-adjusted 10-bit data buffer value (ctrlb.leftadj is one). z bits 5:0 ? reserved these bits are unused and reserved for future use. for compatibility with future devices, always write these bits to zero when this register is written. t hese bits will always return zero when read. bit 151413121110 9 8 databuf[9:2] access r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit76543210 databuf[1:0] accessr/wr/wrrrrrr reset00000000
568 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 32. ptc - peripheral touch controller 32.1 overview the ptc is intended for acquiring capacitive touch sensor and capacitive proximity sensor signals. the external capacitive touch sensor is typically formed on a pcb, and the sensor electrodes are connected to the analog charge integrator of the ptc via device i/o pins. the ptc suppor ts mutual capacitance sensors organized as capacitive touch matrices in different x-y conf igurations, including indium tin oxide (ito) s ensor grids. the ptc requires one pin per x line and one pin per y line. no external components are needed. in self-capacitance mode, the ptc requires just one pin with an x-line driver for each self-capacitance sensor. 32.2 features z implements low-power, high-sensitivity, environmentally robust capacitive touch buttons, sliders, wheels and proximity sensing z supports mutual capacitance and self-capacitance sensing z 16 buttons in self-capacitance mode z 256 buttons in mutual-capacitance mode z one pin per electrode ? no external components z load compensating charge sensing z parasitic capacitance compensation and ad justable gain for superior sensitivity z zero drift over the temperature and vdd range z no need for temperature or vdd compensation z single-shot and free-running charge measurement z hardware noise filtering and noise signal desynchronization for high conducted immunity z selectable channel change delay z allows choosing the settling time on a new channel, as required z acquisition-start triggered by command or interrupt event z interrupt on acquisition-complete z to be used in combination with the atmel ? provided qtouch ? library firmware and qtouch composer tool 32.3 signal description note: 1. the number of x and y lines are device dependent. refer to ?configuration summary? on page 3 for details. refer to ?i/o multiplexing and considerations? on page 15 for details on the pin mapping for this peripheral. one signal can be mapped on several pins. 32.4 product dependencies in order to access the ptc, the user must use the qtouc h composer tool to configure and link the qtouch library firmware with the application code. name type description x[n:0] analog input dac output y[m:0] analog input external reference
569 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 33. packaging information 33.1 thermal considerations 33.1.1 thermal resistance data table 33-1 summarizes the thermal resistance data depending on the package. table 33-1. thermal resistance data 33.1.2 junction temperature the average chip-junction temperature, t j , in c can be obtained from the following equations: equation 1 equation 2 where: z ja = package thermal resistance, junction-to-ambient (c/w), provided in table 33-1 z jc = package thermal resistance, junction-to-case thermal resistance (c/w), provided in table 33-1 z heatsink = cooling device thermal resistance (c/w), provided in the device datasheet z p d = device power consumption (w) z t a = ambient temperature (c) from ?equation 1? , the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. if a cooling device is to be fitted on the chip, ?equation 2? should be used to compute the resulting average chip- junction temperature t j in c. package type ja jc 32-pin tqfp 68 c/w 25.8 c/w 48-pin tqfp 78.8 c/w 12.3 c/w 64-pin tqfp 66.7 c/w 11.9 c/w 32-pin qfn 37.2 c/w 3.1 c/w 48-pin qfn 33 c/w 11.4 c/w 64-pin qfn 33.5 c/w 11.2 c/w t j t a p d ja () + = t j t a p d heatsink jc + () () + =
570 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 33.2 package drawings 33.2.1 64-pin tqfp table 33-2. device and package maximum weight table 33-3. package characteristics table 33-4. package reference 300 mg moisture sensitivity level msl3 jedec drawing reference ms-026 jesd97 classification e3
571 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 33.2.2 64-pin qfn table 33-5. device and package maximum weight table 33-6. package characteristics table 33-7. package reference 200 mg moisture sensitivity level msl3 jedec drawing reference mo-220 jesd97 classification e3
572 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 33.2.3 48-pin tqfp table 33-8. device and package maximum weight table 33-9. package characteristics table 33-10. package reference 140 mg moisture sensitivity level msl3 jedec drawing reference ms-026 jesd97 classification e3
573 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 33.2.4 48-pin qfn table 33-11. device and package maximum weight table 33-12. package characteristics table 33-13. package reference 140 mg moisture sensitivity level msl3 jedec drawing reference mo-220 jesd97 classification e3
574 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 33.2.5 32-pin tqfp table 33-14. device and package maximum weight table 33-15. package characteristics table 33-16. package reference tbd mg moisture sensitivity level msl3 jedec drawing reference ms-026 jesd97 classification e3
575 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 33.2.6 32-pin qfn table 33-17. device and package maximum weight table 33-18. package characteristics table 33-19. package reference tbd mg moisture sensitivity level msl3 jedec drawing reference mo-220 jesd97 classification e3
576 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 33.3 soldering profile table table 33-20 gives the recommended soldering profile from j-std-20. table 33-20. soldering profile a maximum of three reflow passes is allowed per component. 177038 profile feature green package average ramp-up rate (217c to peak) 3c/s max. preheat temperature 175c 25c 150-200c time maintained above 217c 60-150s time within 5c of actual peak temperature 30s peak temperature range 260c ramp-down rate 6c/s max time 25c to peak temperature 8 minutes max.
577 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 34. errata 34.1 revision a 34.1.1 device 1 - if apb clock is stopped and gclk clock is running, apb read access to read-synchronized registers will fr eeze the system. the cpu and the dap ahb-ap are stalled, as a consequen ce debug operation is impossible. 10416 fix/workaround: do not make read access to read-synchronized registers when apb clock is stopped and gclk is running. to recover from this situation, power cycle the device or reset the device using the resetn pin. 34.1.2 gclk 1 - when the gclk generator is enabled(genctrl.genen=1), set as output (genctrl.oe=1) and use a divisi on factor of one (gendiv.div=1 or 0), the gclk_io can be not set as th e expected genctrl.oov value after disabling the gclk genera tor (genctrl.genen=0). 10716 fix/workaround disable the oe request of the gclk generator (genctrl.oe=0) before disabling the gclk generator (genctrl.genen=0). 2 - the gclk generator clock is st uck when disabling the generator and changing the division factor from on e to a different value while the gclk generator is set as output. 10686 when the gclk generator is enabled(genctrl.genen=1), set as output (genctrl.oe=1) and use a division factor of one (gendiv.div=1 or 0), if the division factor is written to a value different of one or zero after disabling the gclk generator (genctrl.genen=0), the gclk generator will be stuck. fix/workaround disable the oe request of the gclk generator (genctrl.oe=0) before disabling the gclk generator (genctrl.genen=0). 3 - lockup in gclk software r eset when a gclk is locked 10645 when a gclk is locked and the generator used by the locked gclk is not the gclk generator 1, issuing a gclk software reset will lock up the gclk with the syncbusy flag always set. fix/workaround do not issue a gclk swrst or map gclk generator 1 to ""locked"" gclks.
578 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 34.1.3 dfll48m 1 - the workaround for this issue would be to wait for lock before enabling the oob interrupt. this way we will still manage to track if the fine value goes out of bounds due to te mperature changes. 10669 34.1.4 evsys 1 - changing the selected generator of a channel can trigger a spurious interrupt/event. 10443 fix/workaround: to change the generator of a channel, first write with edgesel written to zero, then perform a second write with edg esel written to its target value. 34.1.5 sercom 1 - when the sercom is in slave spi mode, the bufovf flag is not automatically cleared when ctrlb.rxen is set to zero. 10563 fix/workaround: the flag must be manually cleared by sw. 34.1.6 adc 1 - no automatic right shift over 16 samples. 10530 fix/workaround: to right shift more than 16 samples, one must use adjres bits to do a manual right shift. the adjres limit at 7 right shift. so, for 1024 samples you can obtain a result on 15 bits minimum. 34.1.7 flash 1 - when cache read mode is set to deterministic (readmode=2), setting cachedis=1 doesn?t gives 0 wait state r ead time on nvm. this gives lower cpu performances. 10830 fix/workaround: when disabling the cache (ctrlb.cachedis=1), the user must also set readmode to 0 (ctrlb.cachedis=0). 2 - when nvmctrl issues erase or write commands cpu hardfault exception may occur. fix/wo rkaround: either turn o ff cache before issuing flash commands or write 0x1 to nv mctrl ctrlb.readmode to set the cache low_power mode. 10804
579 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 35. datasheet revision history please note that the referring page numbers in this section ar e referred to this document. the referring revision in this section are referring to the document revision. 35.1 rev. a ? 06/2013 1. initial revision
580 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 table of contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1. configuration summary . . . . . . . . . . . . . . . . . 3 2. ordering information sam d20 . . . . . . . . . . . 4 2.1 ordering information sam d20e. . . . . . . . . . . . . . 4 2.2 ordering information sam d20g . . . . . . . . . . . . . 5 2.3 ordering information sam d20j . . . . . . . . . . . . . . 6 3. about this document . . . . . . . . . . . . . . . . . . . 7 3.1 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 acronyms and abbreviations. . . . . . . . . . . . . . . . . 8 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . 11 5. pinout diagrams . . . . . . . . . . . . . . . . . . . . . . 12 5.1 sam d20j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 sam d20g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 sam d20e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. i/o multiplexing and considerations . . . . . . 15 6.1 multiplexed signals . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 other functions. . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. signal descriptions list . . . . . . . . . . . . . . . . 18 8. power supply and start-up considerations . 20 8.1 power domain overview. . . . . . . . . . . . . . . . . . . 20 8.2 power supply considerations . . . . . . . . . . . . . . . 20 8.3 start-up considerations . . . . . . . . . . . . . . . . . . . 22 8.4 power-on reset and brown-out detector . . . . . 22 9. . . . . . . . . . . . . . . . . . . . . . product mapping 23 10. memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.1 embedded memories . . . . . . . . . . . . . . . . . . . . . 24 10.2 physical memory map . . . . . . . . . . . . . . . . . . . . . 24 10.3 non-volatile memory (nvm) user row mapping 25 10.4 nvm software calibration row mapping . . . . . . 26 11. processor and architecture . . . . . . . . . . . . . 27 11.1 cortex-m0+ processor . . . . . . . . . . . . . . . . . . . . 27 11.2 nested vector interrupt controller. . . . . . . . . . . . 28 11.3 high-speed bus matrix . . . . . . . . . . . . . . . . . . . . 29 11.4 ahb-apb bridge . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.5 pac ? peripheral access controller . . . . . . . . . . 31 12. peripherals configuration overview . . . . . . . 39
581 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 13. dsu ? device service unit . . . . . . . . . . . . . .41 13.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 13.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 13.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 13.4 signal description. . . . . . . . . . . . . . . . . . . . . . . . 42 13.5 product dependencies . . . . . . . . . . . . . . . . . . . . 42 13.6 debug operation . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.7 chip-erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 13.8 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 13.9 intellectual property protection . . . . . . . . . . . . . . 45 13.10 device identification. . . . . . . . . . . . . . . . . . . . . . . 46 13.11 functional description . . . . . . . . . . . . . . . . . . . . . 47 13.12 register summary . . . . . . . . . . . . . . . . . . . . . . . . 52 13.13 register description . . . . . . . . . . . . . . . . . . . . . . 55 14. clock system . . . . . . . . . . . . . . . . . . . . . . . . .77 14.1 clock distribution. . . . . . . . . . . . . . . . . . . . . . . . . 77 14.2 synchronous and asynchronous clocks . . . . . . . 78 14.3 register synchronization . . . . . . . . . . . . . . . . . . . 78 14.4 enabling a peripheral . . . . . . . . . . . . . . . . . . . . . 81 14.5 on-demand, clock requests. . . . . . . . . . . . . . . . 81 14.6 power consumption vs speed . . . . . . . . . . . . . . 82 14.7 clocks after reset . . . . . . . . . . . . . . . . . . . . . . . . 82 15. gclk ? generic clock controller . . . . . . . . .83 15.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 15.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 15.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 15.4 signal description . . . . . . . . . . . . . . . . . . . . . . . . 84 15.5 product dependencies . . . . . . . . . . . . . . . . . . . . 84 15.6 functional description . . . . . . . . . . . . . . . . . . . . . 85 15.7 register summary . . . . . . . . . . . . . . . . . . . . . . . . 90 15.8 register description . . . . . . . . . . . . . . . . . . . . . . 91 16. pm ? power manager . . . . . . . . . . . . . . . . .105 16.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 16.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 16.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 106 16.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 106 16.5 product dependencies . . . . . . . . . . . . . . . . . . . 106 16.6 functional description . . . . . . . . . . . . . . . . . . . . 108 16.7 register summary . . . . . . . . . . . . . . . . . . . . . . . 115 16.8 register description . . . . . . . . . . . . . . . . . . . . . 117 17. sysctrl ? system controll er . . . . . . . . . .132 17.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 17.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 17.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 133 17.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 134 17.5 product dependencies . . . . . . . . . . . . . . . . . . . 134 17.6 functional description . . . . . . . . . . . . . . . . . . . . 135 17.7 register summary . . . . . . . . . . . . . . . . . . . . . . . 144
582 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 17.8 register description . . . . . . . . . . . . . . . . . . . . . 146 18. wdt ? watchdog timer . . . . . . . . . . . . . . .184 18.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 18.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 18.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 184 18.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 185 18.5 product dependencies . . . . . . . . . . . . . . . . . . . 185 18.6 functional description . . . . . . . . . . . . . . . . . . . . 186 18.7 register summary . . . . . . . . . . . . . . . . . . . . . . . 191 18.8 register description . . . . . . . . . . . . . . . . . . . . . 192 18.9 asynchronous watchdog clock characterization 202 19. rtc ? real-time counter . . . . . . . . . . . . .203 19.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 19.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 19.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 203 19.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 204 19.5 product dependencies . . . . . . . . . . . . . . . . . . . 204 19.6 functional description . . . . . . . . . . . . . . . . . . . . 205 19.7 register summary . . . . . . . . . . . . . . . . . . . . . . . 211 19.8 register description . . . . . . . . . . . . . . . . . . . . . 214 20. eic ? external interrupt controller . . . . . . . .247 20.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 20.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 20.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 247 20.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 248 20.5 product dependencies . . . . . . . . . . . . . . . . . . . 248 20.6 functional description . . . . . . . . . . . . . . . . . . . . 249 20.7 register summary . . . . . . . . . . . . . . . . . . . . . . . 253 20.8 register description . . . . . . . . . . . . . . . . . . . . . 254 21. nvmctrl ? non-volatile memory controller 266 21.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 21.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 21.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 266 21.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 266 21.5 product dependencies . . . . . . . . . . . . . . . . . . . 267 21.6 functional description . . . . . . . . . . . . . . . . . . . . 267 21.7 register summary . . . . . . . . . . . . . . . . . . . . . . 274 21.8 register description . . . . . . . . . . . . . . . . . . . . . 275 22. port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 22.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 22.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 22.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 290 22.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 290 22.5 product dependencies . . . . . . . . . . . . . . . . . . . 290 22.6 functional description . . . . . . . . . . . . . . . . . . . . 292 22.7 register summary . . . . . . . . . . . . . . . . . . . . . . . 297 22.8 register description . . . . . . . . . . . . . . . . . . . . . 299
583 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 23. evsys ? event system . . . . . . . . . . . . . . . .314 23.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 23.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 23.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 315 23.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 315 23.5 product dependencies . . . . . . . . . . . . . . . . . . . 315 23.6 functional description . . . . . . . . . . . . . . . . . . . . 316 23.7 register summary 321 23.8 register description . . . . . . . . . . . . . . . . . . . . . 322 24. sercom ? serial communication interface 337 24.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 24.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 24.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 337 24.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 337 24.5 product dependencies . . . . . . . . . . . . . . . . . . . 338 24.6 functional description . . . . . . . . . . . . . . . . . . . . 339 25. sercom usart ? sercom universal synchronous and asyn- chronous receiver and transmitter 345 25.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 25.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 25.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 346 25.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 346 25.5 product dependencies . . . . . . . . . . . . . . . . . . . 346 25.6 functional description . . . . . . . . . . . . . . . . . . . . 348 25.7 register summary . . . . . . . . . . . . . . . . . . . . . . . 354 25.8 register description . . . . . . . . . . . . . . . . . . . . . 355 26. sercom spi ? sercom serial peripheral interface 369 26.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 26.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 26.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 369 26.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 369 26.5 product dependencies . . . . . . . . . . . . . . . . . . . 370 26.6 functional description . . . . . . . . . . . . . . . . . . . . 371 26.7 register summary . . . . . . . . . . . . . . . . . . . . . . . 378 26.8 register description . . . . . . . . . . . . . . . . . . . . . 379 27. sercom i2c ? sercom inter-integrated circuit 394 27.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 27.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 27.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 394 27.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 395 27.5 product dependencies . . . . . . . . . . . . . . . . . . . 395 27.6 functional description . . . . . . . . . . . . . . . . . . . . 396 27.7 register summary . . . . . . . . . . . . . . . . . . . . . . . 408 27.8 register description . . . . . . . . . . . . . . . . . . . . . 412 28. tc ? timer/counter . . . . . . . . . . . . . . . . . . .441 28.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
584 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 28.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 28.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 442 28.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 443 28.5 product dependencies . . . . . . . . . . . . . . . . . . . 443 28.6 functional description . . . . . . . . . . . . . . . . . . . . 444 28.7 register summary . . . . . . . . . . . . . . . . . . . . . . . 454 28.8 register description . . . . . . . . . . . . . . . . . . . . . 457 29. adc ? analog-to-digital converter . . . . . . .481 29.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 29.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 29.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 482 29.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 482 29.5 product dependencies . . . . . . . . . . . . . . . . . . . 483 29.6 functional description . . . . . . . . . . . . . . . . . . . . 484 29.7 register summary . . . . . . . . . . . . . . . . . . . . . . . 493 29.8 register description . . . . . . . . . . . . . . . . . . . . . 495 30. ac ? analog comparator . . . . . . . . . . . . . .520 30.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 30.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 30.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 521 30.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 521 30.5 product dependencies . . . . . . . . . . . . . . . . . . . 521 30.6 functional description . . . . . . . . . . . . . . . . . . . . 522 30.7 register summary . . . . . . . . . . . . . . . . . . . . . . . 532 30.8 register description . . . . . . . . . . . . . . . . . . . . . 533 31. dac ? digital-to-analog converter . . . . . . .549 31.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 31.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 31.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 549 31.4 signal description . . . . . . . . . . . . . . . . . . . . . . . 549 31.5 product dependencies . . . . . . . . . . . . . . . . . . . 550 31.6 functional description . . . . . . . . . . . . . . . . . . . . 551 31.7 register summary . . . . . . . . . . . . . . . . . . . . . . . 554 31.8 register description . . . . . . . . . . . . . . . . . . . . . 555 32. ptc - peripheral touch controller . . . . . . . .568 32.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 32.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 32.3 signal description . . . . . . . . . . . . . . . . . . . . . . . 568 32.4 product dependencies . . . . . . . . . . . . . . . . . . . 568 33. packaging information . . . . . . . . . . . . . . . . .569 33.1 thermal considerations. . . . . . . . . . . . . . . . . . . 569 33.2 package drawings. . . . . . . . . . . . . . . . . . . . . . . 570 33.3 soldering profile . . . . . . . . . . . . . . . . . . . . . . . . 576 34. errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .577 34.1 revision a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
585 atmel sam d20 [preliminary datasheet] 42129a?sam?06/2013 35. datasheet revision history . . . . . . . . . . . . .579 35.1 rev. a ? 06/2013 . . . . . . . . . . . . . . . . . . . . . . . . 579 table of contents . . . . . . . . . . . . . . . . . . . . . . . .580
atmel corporation 1600 technology drive san jose, ca 95110 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 www.atmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong roa kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan g.k. 16f shin-osaki kangyo bldg 1-6-4 osaki, shinagawa-ku tokyo 141-0032 japan tel: (+81) (3) 6417-0300 fax: (+81) (3) 6417-0370 ? 2013 atmel corporation. all rights reserved. / rev.: 42129a?sam?06/2013 disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. exce pt as set forth in the atmel terms and conditions of sales locat ed on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not li mited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any d irect, indirect, consequential, punitive, special or incide ntal damages (including, without limitation, damages for loss and profits, business i nterruption, or loss of information) arising out of the use or inab ility to use this document, even if atmel has been advised of the possibility of suc h damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to update the information contained herein. unless specifically provided oth erwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applications intend ed to support or sustain life. atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , qtouch ? , and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. arm ? , cortex ? and others are registered trademarks or trademarks of arm ltd. other terms and product names may be trademarks of others.

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